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Oscillations at a phase margin of 90?

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I have a similar guess as LvW. Possibly you got more than one loop in LDO. Some loop might be obscure. For multi-loop, you must make all loops have enough phase margin to make it stable. So probing AC characteristics at different places is needed.

Added after 18 minutes:

Would you post your schematic?
 

I can't post the schematic.

I've looked once more on the schematic and I don't think its a hidden-loop problem; I've added the IPROBE between the output node and the negative feedback point of the error amplifier's input, so its not a problem of where I put the IPROBE. All the internal circuits used are stable. I don't really know what going on :|
 

What is the orientation of the PMOS ?
Common source or common drain arrangement ? The question is important because both configurations have different stability properties.

Added after 31 minutes:

Forget my last question.
As you use a PMOS device it will work in common source operation with Vdrain=Vin and Vout=Vsource.
Only to be sure: The reference voltage is connected to the inverting and the signal from the resistive divider to the noninv. opamp terminal, right ?
 

Yes, its a common source with the source connected to the unregulated voltage and the drain gives the required regulated output.

About the error amplifier. It is as you said.

LvW said:
What is the orientation of the PMOS ?
Common source or common drain arrangement ? The question is important because both configurations have different stability properties.

Added after 31 minutes:

Forget my last question.
As you use a PMOS device it will work in common source operation with Vdrain=Vin and Vout=Vsource.
Only to be sure: The reference voltage is connected to the inverting and the signal from the resistive divider to the noninv. opamp terminal, right ?
 

There is something which came into my mind just now:

When we require to ground the input signal during loop gain (i.e. stability) analysis, you should take care of a correct bias point of course.

To be specific: The drain should be connected to the unregulated voltage also during loop gain simulation (otherwise there would be no VDS); and the input signal which must be zero during this simulation is just the CHANGE of this voltage.

With other words: ΔVin=0 means Vin=constant.

I suppose, you have taken care of this, don´t you ?
 

what are the settings of ur transient simulation testbench
 

Yes, all the voltages at the stability analysis are set to a DC value only. i.e. I perform the stability analysis on a properly DC biased circuit.

But I don't know why you want to set the drain to the unregulated voltage? The PMOS is in a common source configuration where the source should be connected to the unregulated voltage and the drain should be the only which supplies the regulated voltage?

What I understand is that the signals should be AC grounded, not actual ground, i.e. in the stability analysis, we only need the AC components to be zero.

LvW said:
There is something which came into my mind just now:

When we require to ground the input signal during loop gain (i.e. stability) analysis, you should take care of a correct bias point of course.

To be specific: The drain should be connected to the unregulated voltage also during loop gain simulation (otherwise there would be no VDS); and the input signal which must be zero during this simulation is just the CHANGE of this voltage.

With other words: ΔVin=0 means Vin=constant.

I suppose, you have taken care of this, don´t you ?

Added after 1 minutes:

I'm performing a transient simulation to check the start up of the circuit so its only a transient simulation with conservative accuracy.

safwatonline said:
what are the settings of ur transient simulation testbench
 

ok, what i mean is:
1- usually when Transient shows oscillation then you are unstable (i.e. trust the tran sim.)
2- if AC shows stable operation then most probably there is difference between transient simulation and AC (i.e. AC is small signal analysis around some DC operating point, so i guess the AC is at a stable operating point while the tran passed through some unstable operating point)
3- so as a suggestion maybe you divide the start-up into some steps (i.e. if u are ramping the supply then do smaller ramps, if u r stepping the load current also do smaller steps, also try to reverse the step direction i.e. from higher current to lower ...etc) this is done to try to get the boundary of oscillation, which means when the circuit exactly starts to oscillate (then once u know that point u should do AC analysis on this point)

tab3an elkalam dah kolo kalam fare3' matsada2sh 2y 7aga menoo :D , w ba3deen 2oom zaker w seebak men eldesign delwa2ty :D
 

Quote elmolla: But I don't know why you want to set the drain to the unregulated voltage? The PMOS is in a common source configuration where the source should be connected to the unregulated voltage and the drain should be the only which supplies the regulated voltage?

You are right, sorry - I have mixed source and drain.

Added after 19 minutes:

Hi elmolla:
Do you mind showing us a diagram of the BODE diagram for loop gain (magnitude and phase) ?
 

Hi Emolla

just check the saturation margins of the devices in ur design...

if its low then a transient pulse/step can throw ur device out of saturation and it might never recover back reulting into oscillations.

So take a operating point calulation from ur transinent sims.
 

I'm sorry LvW, I can't post anything related to the circuit; Thats why I'm trying to be as descriptive as possible.


LvW said:
Quote elmolla: But I don't know why you want to set the drain to the unregulated voltage? The PMOS is in a common source configuration where the source should be connected to the unregulated voltage and the drain should be the only which supplies the regulated voltage?

You are right, sorry - I have mixed source and drain.

Added after 19 minutes:

Hi elmolla:
Do you mind showing us a diagram of the BODE diagram for loop gain (magnitude
and phase) ?

Added after 7 minutes:

I agree with the point that transient is more trustworthy than AC analysis.

I actually find your point very interesting, you mean the AC analysis could've been done on a stable DC operating point while the transient is on an unstable one. Well, this makes sense, but how it would this happen if both circuits are at the same loading? Actually, the oscillatory behavior's average is very close to the calculated DC point.

I understand I may have more than one operating point, but the unwanted one is far beyond the one I'm monitoring; If this isn't the case, then only the ramp simulation could show me all the operating points?

7ader ya basha :) Ha2om azaker we asebny mel design. Rabena ma3ak bokra ya kabeer :D

safwatonline said:
ok, what i mean is:
1- usually when Transient shows oscillation then you are unstable (i.e. trust the tran sim.)
2- if AC shows stable operation then most probably there is difference between transient simulation and AC (i.e. AC is small signal analysis around some DC operating point, so i guess the AC is at a stable operating point while the tran passed through some unstable operating point)
3- so as a suggestion maybe you divide the start-up into some steps (i.e. if u are ramping the supply then do smaller ramps, if u r stepping the load current also do smaller steps, also try to reverse the step direction i.e. from higher current to lower ...etc) this is done to try to get the boundary of oscillation, which means when the circuit exactly starts to oscillate (then once u know that point u should do AC analysis on this point)

tab3an elkalam dah kolo kalam fare3' matsada2sh 2y 7aga menoo :D , w ba3deen 2oom zaker w seebak men eldesign delwa2ty :D
:D

Added after 2 minutes:


What do you mean by the saturation margins ashish?

Do you mean keeping the voltage levels at the device to keep it operate in saturation Don't worry about this. All the voltage levels corresponds to devices operating in saturation.

ashish_chauhan said:
Hi Emolla

just check the saturation margins of the devices in ur design...

if its low then a transient pulse/step can throw ur device out of saturation and it might never recover back reulting into oscillations.

So take a operating point calulation from ur transinent sims.

Added after 1 minutes:

I've done another simulation of load switching between a stable and unstable point. The oscillations aren't altered! It just keeps in a state of sustained oscillations of peak to peak value about 8% around the stable operating point, even after passing through he stable operating loading:!::!::!:
 

By saturation margins I mean ur devices shud be having enough vds as compared to vdsat...

vds shud not be marginally greater than vdsat...

Added after 2 minutes:

"I've done another simulation of load switching between a stable and unstable point. The oscillations aren't altered! It just keeps in a state of sustained oscillations of peak to peak value about 8% around the stable operating point, even after passing through he stable operating loading:!: "

Then probably I am pointing in right direction.
 

Did you check the gain margin?

Phase Margin is not enough for ensuring stable operation in systems with multiple zeroes and poles. You must have a high enough phase and gain margins
 

That´s correct. Good idea. One should have known earlier.
 

All the transistors are operating deep in saturation during the operation region of interest as I've mentioned before. I've checked that. :|


ashish_chauhan said:
By saturation margins I mean ur devices shud be having enough vds as compared to vdsat...

vds shud not be marginally greater than vdsat...

Added after 2 minutes:

"I've done another simulation of load switching between a stable and unstable point. The oscillations aren't altered! It just keeps in a state of sustained oscillations of peak to peak value about 8% around the stable operating point, even after passing through he stable operating loading:!: "

Then probably I am pointing in right direction.

Added after 4 minutes:

I've checked the gain margin; The gain at the phase cross over point is around -24 dB ~ -26 dB.

I think I'm different with you at this point. What I understand is that the phase margin or gain margin is enough to measure the stability; The phase margin is more used as it gives us a measure of the step response of the system and its ringing or oscillatory behavior, while the gain margin is only of relevance to see if the system is stable or not and if its unstable, then what will the amplitude of oscillations will be.

Am I right with that?

elbadry said:
Did you check the gain margin?

Phase Margin is not enough for ensuring stable operation in systems with multiple
zeroes and poles. You must have a high enough phase and gain margins

Added after 47 seconds:

LvW said:
That´s correct. Good idea. One should have known earlier.

Do you mean the gain margin or the saturation check?
 

Do you mean the gain margin or the saturation check?

My remark was directed to simulation of the gain margin. It was and it is a good idea to check this - in addition to the PM - as you have severe problems in finding the source of some discrepancies. OK, and the GM also indicates stabilty. That´s no solution of the problem but an additional confirmation that something is wrong within your circuit.
By the way, it was new to me to hear from you that "all the transistors....".
From this I conclude that also the error amplifier is developed by you, instead of using a commercial opamp.
There is a certain probability that the instabilty is generated in this amplifier which circuitry is unknown to the participants of this forum.
 

Without schematic, you can't be helped.
 

OK LvW. I'm with you about that GM is important, thats why I had checked it :D and I've pointed out that it isn't the problem. I have a gain margin of 24-26 dB as I've pointed earlier (Gain at the phase cross over point is -24~-26dB), so there seems no problem I guess.. :|

I feel a misconception here LvW; How would I use a commercial opamp in an analog IC design? This isn't a discrete circuits, it is integrated.

I know showing the schematic would help a lot but I can't show the schematic as I've pointed before.

There is nothing special about the error amplifier I'm using, its a simple differential pair loaded by a current mirror for a single ended output, followed by a buffer to drive the PMOS pass device. Anyone familiar with Analog IC design knows this circuit.

I've checked the error amplifier and buffer before; I checked their stability together and they are fine.

I think we could better pin point the problem in thinking in a different way;

1. If the circuit is unstable: We'll get oscillations that grow in amplitude till they reach the supply.
2. If the circuit is unstable: We'll get either no oscillations or damped oscillating behavior depending on the phase margin.
3. What kind of a system will give us sustained oscillations around the STEADY STATE DC with an amplitude that is 8~10% of the steady state value? Not peak to peak oscillations?
 

elmolla said:
I feel a misconception here LvW; How would I use a commercial opamp in an analog IC design? This isn't a discrete circuits, it is integrated.

I know showing the schematic would help a lot but I can't show the schematic as I've pointed before.

Sorry, I didn´t realize at the moment of writing that you are designing an IC by yourself. Perhaps I have mixed some ideas and information with other forum topics.

Nevertheless, why can´t you scetch the principal response of the open loop gain and phase ? It is not necessary to see the real simulation results, but a diagram showing the principal response (only asymptotic) could perhaps reveal some hidden things - who knows.
Otherwise I resign.
 

It is not neccesary that you always have rail to rail oscillations...

something or other can limit the amplitudes of oscillation(like what we can do in intentional oscillators)
 

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