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You didn't say what you are sampling, but you can generate a 125 MHz (8ns) clock by instantiating a DCM (digital clock manager) into your HDL, and then configure its frequency synthesizer (the CLKFX output) to multiply the board's 50 MHz clock by the ratio 5/2.
I used Clocking Wizard to initiate the DCM
when I assign the CLK2X_OUT to my OUTCLK port, I couldnt see anything when I simulate it in ModelSim. But when I assign CLK0_OUT instead, I can see the waves... am I on the right track?
I don't know. Maybe 9.2i or your simulator has a bug. Be sure you've installed the latest ISE service pack. If you are using ModelSim, be sure to use a version that's approved by Xilinx (although I usually don't have problems using different versions).
Your clock appears to be 5 MHz instead of 50 MHz. I don't know why. Maybe your main_tbw.tbw file is involved, but I don't know how to use it. I generate clocks with a Verilog testbench.
Before the DCM locks, it can output glitches and other ugly pulses. If that causes you grief, read about the DCM's LOCKED output signal, and the STARTUP_WAIT attribute.
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