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How important is the check_design command for synthesis in DC?

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ASIC_intl

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How important is the check_design command for synthesis?

After doing check_design I FIND THERE ARE SOME PROBLEMS IN MY DESIGN. The report generated after check_design contain name of some instances and also nets that are not present in the design file. I am using the check_design command before compilation. How to see these problems whose correponding instance and net name are not present in the RTL which ere analyzed and elaborated.
 

check_design, design compiler

Hi,
Make sure that you read all the modules of your verilog netlist.

Thanks
Chaitanya
 

synthesis check_design

All the modules have been read.
 

Re: design compiler

The warnings generated by check_design command are important and should be carefully analysed before u neglect them, if u r the designer for that particular block, u should be knowing the gate inference from that RTL code. Isn't it??
 

Re: design compiler

The code os too big to understand all the instances of it. Again the name of the instances reported by check_design command are not present as an instance in the complete design. We do not know the blocks which are inferred by those functions.
 

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