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Problem with one clock cycle delay of Sscan D Flip Flop output

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rinaishlene

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Hi
I'm designing a scan D Flip Flop by schematics.The problem is when I simulated the design,the output obtained is delayed by one clock cycle.I'm using Cadence IC Design tool to design the flip flop and using HSPICE to simulate the design.

Is the delay occur because of the design (from the schematic drawn),or from the setup and hold time or any other settting that must be taking place when using HSPICE to simulate the design.

If the delay occur because of the schematics design,would it be better to redesign the schematics by applying Kmap to further simplify the design or redesign the schematics by calculating its logical effort?
 

Re: Scan D Flip Flop

rinaishlene said:
Hi
I'm designing a scan D Flip Flop by schematics.The problem is when I simulated the design,the output obtained is delayed by one clock cycle.I'm using Cadence IC Design tool to design the flip flop and using HSPICE to simulate the design.

Is the delay occur because of the design (from the schematic drawn),or from the setup and hold time or any other settting that must be taking place when using HSPICE to simulate the design.

If the delay occur because of the schematics design,would it be better to redesign the schematics by applying Kmap to further simplify the design or redesign the schematics by calculating its logical effort?
Click to expand...

Post your rtl and will see :)
 

Scan D Flip Flop

If I understand the post, he didn't care RTL, just the schematics.

Post your schematic.
 

Re: Scan D Flip Flop

Below is the image of the schematics



Added after 2 hours 51 minutes:


Here is the waveform generated for the scan flip flop
 

Re: Scan D Flip Flop

It looks perfectly OK! While applying inputs w.r.t. clk you have not given any setup time.
Change ur inputs when the clock transitions from high to low and see the results.
 

Re: Scan D Flip Flop

OK...but I don't think it follows the truth table

 

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