Can i use Matlab(Simulink)as data source to FPGAVirtexII pro

Dear all

Can i use Matlab (Simulink)as data source to FPGAVirtexII pro??

and if so , what can i do ,and what is needed? ,if any materials or any other help ,it will be appreciated

thanks in advance

Added after 11 minutes:

also i have an inquiry ,is it possible to use the Ethernet interface in spartan III or virtex II for a real time application ??

how can it be ??

Using HIL(hardware in loop) u can make your simulink data as source to your FPGA.
You need DSP Builder if u ar using Altera,
If u use Xilink System Generator is required.

But simulations runs at JTAG clock.

Don't forget to press help button.

Re: Can i use Matlab(Simulink)as data source to FPGAVirtexII

You need to use System Generator
Feel free to ask me about it, I'm working with it these days...

Regards,
Salma

Re: Can i use Matlab(Simulink)as data source to FPGAVirtexII

salma ali bakr said:

You need to use System Generator
Feel free to ask me about it, I'm working with it these days...

Regards,
Salma

Click to expand...

So is system-generator just a co-simulation linker between Simulink and an HDL-simulator? Or does it do more (like help you write synthesizeable VHDL/Verilog code?)

Sorry, I'm just a little confused between AccelDSP and System Generator -- it sounds ike they have some overlap.

Re: Can i use Matlab(Simulink)as data source to FPGAVirtexII

When System Generator is installed, you have specific Xilinx blocksets in Simulink.
These, and only these, blocksets can be converted into HDL code. So, it is not just for simulation, it can actually create synthesizeable code ....

Note that you can still use the normal Simulink blocksets, but these can never be converted into HDL code. Gateways are used to connect the standard Simulink blocksets to the Xilinx blocksets. These are basically nothing more than converters (converting the Simulink 'doubles' to/from the fixed-point the Xilinx blocksets use).
This way you can use a normal Simulink source, like a sine-wave generator, and a normal Simulink sink, like the scope, to provide and visualize data to/from the Xilinx blocksets. Even when converting into HDL code these gateways can assist you by using hardware co-simulation. The HDL code is then run in the actual FPGA and Simulink provides/visualizes the data (data is passed to/from the gateways using the JTAG or ethernet connection to the FPGA).

There are also Xilinx blocksets that allow you to include your/external HDL code in Simulink by using a black box. Also, you can use a, limited sub-set of, M-code. This can be usefull for state machines and such.

Re: Can i use Matlab(Simulink)as data source to FPGAVirtexII

boardlanguage said:

salma ali bakr said:

You need to use System Generator
Feel free to ask me about it, I'm working with it these days...

Regards,
Salma

Click to expand...

So is system-generator just a co-simulation linker between Simulink and an HDL-simulator? Or does it do more (like help you write synthesizeable VHDL/Verilog code?)

Sorry, I'm just a little confused between AccelDSP and System Generator -- it sounds ike they have some overlap.

Click to expand...

with system generator you can create block level design...which can be converted to HDL netlist or bitstream...

the block level simulations can be done in wavescope, which is an integrated simulator...

for the functional simulation of the generated HDL code, you can just use modelsim for instance! (take into account that the generated HDL code is some sort of spaghetti code, since it employs cores from core generator!!)

you can then take this code to ISE and do the synthesis, place and route, etc etc till generating the bitfile to be downloaded on the FPGA...or else, just generate the bitfile from system generator itself by choosing the bitstream option..\

in system generator you can do hardware co-simulation also, which means that you simulate the design in software (the simulink environment of matlab) or simulate it on the actual hardware...so you use it to compare the results and know whether the hardware is functionally correct or not....and you can use it for reducing simulation time by doing the hardware simulation only and observing the results...

regarding acceldsp, it's integrated with system generator...and helps in synthesizing the algorithmic level design in matlab to RTL ...and generates an IP block, which is then added to a system generator model to make a complete system which can be simulated, used to generate netlist or bitfile, etc etc...so acceldsp can't be standalone, it's always integrated with system generator and only provides this extra [matlab to RTL] part which wasn't available before!!