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Is there a project that cannot be done in VHDL but only in ABEL for CPLDs?

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hi

is there a project or high-level functionality what can not be done in VHDL, only in ABEL for CPLDs?

I am not asking about low-level details, like resetting a flip-flop, but for example producing the same signal sequence on pins, or similar cases...
my colleague told me, most of our board-glue-logic projects must be done in ABEL, because they couldnt make the same functionality (I dont know if they ment only low-level only or high level too, like board level glue logic function) in VHDL.
 

ABEL and VHDL

I have never encountered such a situation.

The HDL synthesis software may not be able to infer some special features of the device (for example Xilinx XST can't infer a DDR flip-flop), however the software always gives you another means of using the feature, such as by instantiating a library primitive or applying an HDL attribute.
 

Re: ABEL and VHDL

I think, this depends on the vendor libraries reflecting the particular hardware. Altera e. g. has HDL libraries for hardware primitives as IO cells, that allow to control any possible parameter. Additional synthesis attributes are present for some settings.
 

ABEL and VHDL

it was ISE.
my colleague said there is no free primitive library for VHDL in ISE free webpack for that. It was a glue logic on a processor board, providing some reset, and power on-sequencing.

but my question is, do we need to have those libraries to make the same functional device?
do we really need for example instantiate a DDR flip-flop? or maybe we can work it out just with the normal language tricks?
 

ABEL and VHDL

Oops, please disregard what I said earlier. I just noticed that you said CPLD and I was thinking FPGA. Sorry. CPLD tools may be different from FPGA tools.
 

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