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It may be easier to write an I2C master (or slave) from the scratch than spending time for understanding and adapting a possible long-winded solution.
I didn't understand clearly, what's the role of CPLD in this case? Is it used for level translation purposes? The I2C core could be implemented in CPLD as well, but it's easier to debug in FPGA with tools as SignalTap or Chipscope. Also the FPGA to CPLD interface is smaller then. Basically a I2C master needs two open drain drivers (can be discrete transistors, too) and a receiver for SDA. SCL has to be sensed only if clock stretching is implemented (most likely not).
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