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i am new with vcs mx.i have verilog at top level and vhdl file are bellow it .i could not able to run it .what i have to do for compiling those vhdl files ?
I am not very shure .... but there is a command +vhdlan and few more to run that command.I used that couple of years back . I will let you know very soon thanks for reminding me
There are several ways to simulate your files... 1st : Using Mix simulation of both VHDL and Verilog ...
2nd : Better for design reuse, you use design compiler to convert either all VHDL files into Verilog or all Verilog files into VHDL and write testbench to simulate your top module.
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