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question about this.ports in systemverilog

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THUNDERRr

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what is meant by this.ports in?
rts


function new (virtual port_nme ports)
begin
this.ports=ports
end
end function

this.ports refere to what?
 

THUNDERRr said:
what is meant by this.ports in?
rts


function new (virtual port_nme ports)
begin
this.ports=ports
end
end function

this.ports refere to what?
Click to expand...

It is like in C++ - it refers to class level variables/properties. In your case "ports" is visible in 2 contexts:

Code: 
function new (virtual port_nme ports)

A local variable called "ports" visible inside the function alone

Code: 
class c;
virtual port_name ports;
function new (virtual port_nme ports)
begin
this.ports=ports
end
endfunction

The keyword "this" unambiguouly points to the "ports" at class level.

We cover these and related topics in our VSV class, see: https://sv-verif.blogspot.com

HTH
Ajeetha, CVC
www.noveldv.com
 

"this" is used to assign a class variable from a local varable having identical names.
 

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