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Need code for generating clock doubler using DCM...

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instantiate dcm block

The section "Compiling Xilinx Simulation Libraries" is on page 234 of the ISE 8.1i Synthesis and Simulation Design Guide.
https://www.xilinx.com/support/sw_manuals/xilinx8/download/sim.zip

Which version of ModelSim do you have? Is it PE, SE, XE, ... ?
I think XE includes pre-compiled libraries, but the other vesions do not, so you must compile them.
 

dcm double clock

Hi,

I am using modelsim SE 6.1b. Compling means normal way of compling or something diff.... I did compling before simulating....it was successful.
 

generate component dcm without feedback

No, compiling the simulation libraries as described in the Xilinx manual is a special operation that takes many minutes and generates a huge directory of files.

Also, whenever you update your ISE or ModelSim installation, you probably should recompile these libraries.
 

dcm behavial simulation

Hi,

I have complied all the simluation libraries-unisim,simprim, xilinx corelib... I am not getting DCM output itself I mean to say double the clock freq(clk2x). I am able to get clko. Do I need to make any changes in the DCM generated by ISE, could u plz look into the waveform and let me know where I have gone wrong.




Added after 35 minutes:

Hi,

I have one doubt, the DCM code generated by ISE consists of one more DCM INST in it. Do I need to port map those to Top module or main DCM ports? When I have portmapped top module with DCM main ports, I am getting error as mutilple drivers. When I portmap with DCM INST and defparam dcm100.CLKIN PERIOD = 20.0; being declared in the topmodule I am getting error as
expecting '=', found 'PERIOD'...

Could u plz tell me any error in the code generated by DCM. And which ports do I need to instatiate in my top module.
 

dcm wizard 40mhz form 50 mhz

Ok, good job compiling the libraries.

Your JPEG image is helpful, but it doesn't show the time axis. Be sure your clock is really 50 MHz (20ns).

Please upload your current source code and testbench. I can't quite follow your description about ports, and I can't guess what code your version of ISE has generated, or which options you've selected.

My defparam statement works with a DCM primitive. It probably won't work with some module generated by ISE.
 

verilog example using dcm

when I compile my top module I am getting the error as....

ERROR:Xst:528 - Multi-source in Unit <clock2x> on signal <clk50dcm>,

we have clk50 for both drivers. And output is not generated for clock2x from DCM. Plz find the attached files of my code.
 

dcm ise simulation fail

I see some problems in your clock2x module:
- Signal clk50dcm shorts together two output ports.
- Too many BUFGs. The dcm2x module already buffers the 100 MHz clock.
- Verilog is case-sensitive. Change 'LOCKED' to 'locked'.

Try this. It simulates fine with your dcm2x and testbench modules:
Code:
module clock2x (clk50, count, locked);
  input             clk50;      // synthesis attribute period clk "50 MHz";
  wire              clk100;
  output reg  [7:0] count = 0;
  output            locked;

  dcm2x dcm100 (.CLKIN_IN(clk50), .RST_IN(1'b0), .CLKIN_IBUFG_OUT(), .CLK0_OUT(), .CLK2X_OUT(clk100),.LOCKED_OUT(locked));

  always @ (posedge clk100)
  begin
    count <= count + 1;
  end
endmodule
 

instantiating the dcm unit

Its not working, when I simulate the DCM I am not getting outputs for clk2x,locked signals. when I wont get output in DCM, the same I am instatiating in Clock2x top module. Thus I am getting error output in both of these. One more query I am using testbench na do I need to force clock in DCM? These are my latest waveforms of DCM and clock2x, after changes made acc to u....



 

dcm-to-dcm xilinx

I don't know why it doesn't work for you. Maybe your version of ISE has a bug. Be sure you've installed the latest service packs.

Also try applying a reset pulse to the DCM. The pulse duration should be at least three clock cycles.
 

dcm to dcm cascade virtex 5

Hi,

I didn't understand u r talking about which pulse duration?

The pulse duration should be at least three clock cycles?

Added after 4 minutes:

I didnt understand u r talking about which clock pulse duration?

The pulse duration should be at least three clock cycles?
 

warning: (vsim-3473)

"Also try applying a reset pulse to the DCM."

That's the RST_IN port of dcm2x.


I hope that solves the problem, because I have no more guesses!
 

dcm clock loading

Hi,

I tried to generate my dcm with vhdl in my friends sytem its working fine but not in verilog. But I dont have option to select lang preference in my system. I have asked for service pack of ISE 8.1i. Is there any other chances?

Added after 5 hours 54 minutes:

I have a doubt why do we need counter in the top module. I have one more doubt I have generated dcm using ISE 9.1i (Institute system) in VHDL but its not working with ISE 8.1i. Does it make any diff...? In 8.1i version I don't have any option to generate dcm using vhdl mean dont have option to select lang preference...
 

modelsim dcm_sp

Good to hear that you have seen partial success. You may be closer to solving the problem.

Over the years, I've seen a variety of problems with Xilinx DCM simulation models, even as recently as version 10.1. For example, this problem occurs in VHDL but works fine in Verilog:


If you have good internet bandwidth, you can download ISE service packs here. Use the "Modify Search" to select your ISE version:
http://www.xilinx.com/support/download/index.htm

Mixing code from different versions of Xilinx tools sometimes causes problems. I'm not surprised that 8.1 didn't like the 9.1 DCM.

You are correct that my counter isn't necessary. I put it into the top module simply to give the clock something useful to do!


Other options:

If you are a commercial ISE customer or a professor (but not a student), you can submit a WebCase question to the Xilinx customer support team.
http://www.xilinx.com/support/clearexpress/websupport.htm

If you are a student or hobbyist, you can try asking your question in the Xilinx support forum:
http://forums.xilinx.com/
 

xilinx dcm spartan vhdl instance

Hi

I have installed service pack for ISE 8.1i,but then I dont have option to generate my DCM in VHDL.I am running the code generated by 10.1i.I am not getting the output i.e, clock2x from my DCM. Please let me know if I have to make any changes in DCM module.I believe there is any port connection missing for clock2x output.I got perfect output in 10.1i, for the same code.Find attached file which consists code for DCM , top module and o/p waveform of DCM.

 

xilinx dcm_sp cascade

Hi,

I was not getting output in 8.1i. I have downloaded webpack 10.1. I am getting partial output. I am not getting locked out o/p and o/p clk is does not have 50% duty cycle. Another thing there is no component declaration in the code generated by webpack. However it is present in 10.1i licensed version. Then i added the component declaration into code. But no improvements. Plz let me know if u have any idea where its going wrong....I am very thankful for ur guidelines n encouragement.

 

dcm wizard webpack

You mentioned using Spartan-3. Are you sure you've selected Spartan-3 in your project? Your code contains a DCM_SP, and Spartan-3 only provides DCM.
 

dcm clk0 and clk2x

yeah I have selected spartan 3 and spartan 3E(when i didnt get thro' spartan 3).
with which device DCM_SP will be generated?
 

vsim 3473

Spartan-3 has DCM.

Spartan-3E, -3A, and -3A DSP have DCM_SP. If you use DCM with one of these FPGAs, ISE should automatically substitute a DCM_SP during synthesis.

Uh-oh, now it's broken for me. One of my previously working projects is now generating bad CLK2X. I recently upgraded to ISE 10.1.02 and ModelSim 6.4. I don't yet know which upgrade is causing the malfunction. If I use 1X feedback instead of 2X feedback, or if I use DCM instead of DCM_SP, the CLK2X output starts working again.
 

dcm_sp_inst

Acc to datasheets if i need clock2x output i need to give clock2x as feedback....so i was going in that way. However even my friend tried with 1x feedback in her office, she is getting output. even i tried to change to 1x but no improvements. One more doubt my OS is pirated one does it matter?
 

ise bug multi-source in unit on signal

Yes, "2X" feedback mode requires CLK2X signal feedback. "1X" feedback mode requires CLK0 signal feedback. Well, that's the way it *should* behave.

I don't think bootleg will cause this problem. ;)
 

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