Need code for generating clock doubler using DCM...

Re: xilinx dcm vhdl

echo47 said:

I can't quite understand your second message, sorry.

I don't know VHDL very well, but maybe this Verilog example will help you. It inputs a 50 MHz clock, doubles it to 100 MHz, and then clocks a simple counter. It synthesizes into a Spartan-3, a Virtex-5, and maybe other FPGA types too.

Code:

module top (clk50, count);
  input             clk50;      // synthesis attribute period clk "50 MHz";
  wire              clk50dcm, clk100dcm, clk100;
  output reg  [7:0] count = 0;

  DCM dcm100 (.CLKIN(clk50), .RST(1'b0), .CLKFB(clk50dcm), .CLK0(clk50dcm), .CLK2X(clk100dcm));
  defparam dcm100.CLKIN_PERIOD = 20.0;
  BUFG buf100 (.I(clk100dcm), .O(clk100));

  always @ (posedge clk100) begin
    count <= count + 1;
  end
endmodule

That's only an example. The DCM is highly configurable, so be sure to read the user guide and data sheet for your FPGA, and use whichever DCM connections and parameters are appropriate for your project. Some folks prefer to use the wizard instead because it hides many of those details.

Click to expand...

hi in synthesis and simulation part this no issues but while implement in to the spartan 3an FPGA it provides only CLK50 output .......

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Lokesh Waran said:

hi in synthesis and simulation part this no issues but while implement in to the spartan 3an FPGA it provides only CLK50 output .......

Click to expand...

i changed the codings like this........

`timescale 1ns / 1ps

module DCM_CLOCK (CLK,CLK50DCM,RST_IN,CLK100,LOCKED_OUT);

input CLK,RST_IN;
output CLK50DCM,CLK100,LOCKED_OUT;


reg [7:0] count = 0;

wire RST_IN;
wire CLK_IN;

wire CLK50DCM, CLK100DCM, CLK100,LOCKED_OUT;
reg CLK50;


DCM_CLK instance_name (
.CLKIN_IN(CLK50),
.RST_IN(RST_IN),
.CLK0_OUT(CLK50DCM),
.CLK2X_OUT(CLK100DCM),
.LOCKED_OUT(LOCKED_OUT)
);

BUFG buf100 (.I(CLK100DCM),.O(CLK100));

always @ (posedge CLK) begin
count <= count + 1;
if(count<=9)
CLK50<=1;
if(count>=10)
CLK50<=0;
if(count>=19)
count<=0;
end
endmodule