govandi999
Newbie level 4
challenging vhdl designs
Design a Password feeder using behavioral VHDL. In this we have an 8-bit input DATA for the password. We have a signal called ENABLE. If ENABLE ='1' then the input data ie the password is read and loaded in a register. The input DATA is then compared to the data stored in a variable somewhere inside the code. 3 chances are given. if it fails three times then the output should display 'E' (Fail) on the seven segment decoder and if the password is correct, it should display 'S' (Pass)
Design a Password feeder using behavioral VHDL. In this we have an 8-bit input DATA for the password. We have a signal called ENABLE. If ENABLE ='1' then the input data ie the password is read and loaded in a register. The input DATA is then compared to the data stored in a variable somewhere inside the code. 3 chances are given. if it fails three times then the output should display 'E' (Fail) on the seven segment decoder and if the password is correct, it should display 'S' (Pass)