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  1. #1
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    validation of AES core

    i am working on implementation of AES on FPGA,i have made it's core and simulate it, now i am interested to check validity of my core after implementation on FPGA. kindly suggest me, that how can i check my core performance after implemented it in FPGA.


    regards

    kzirshan

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  2. #2
    Full Member level 2
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    7 years registered

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    Re: validation of AES core

    I think the performance of the core depends on the maximum clock used by your design. The maximum clock can be calculated by the compiler.



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