Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

validation of AES core

Status
Not open for further replies.

kzirshan

Newbie level 2
Joined
Jun 11, 2008
Messages
2
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,296
i am working on implementation of AES on FPGA,i have made it's core and simulate it, now i am interested to check validity of my core after implementation on FPGA. kindly suggest me, that how can i check my core performance after implemented it in FPGA.


regards

kzirshan
 

I think the performance of the core depends on the maximum clock used by your design. The maximum clock can be calculated by the compiler.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top