Mirzaaur
Member level 2
Dear all,
I have a doubt about declaring the type for state variables. normall its declared as :
type sm is (sate1, stae2, stae3...);
signal pr_st, nxt_st: sm;
what difference it will make in synthesis or function of circuit if its done like this way
constant sate1 : std_logic_vector(2 downto 0) := "000";
constant state2 : std_logic_vector(2 downto 0) := "001";
constant state3 : std_logic_vector(2 downto 0) := "011";
constant state4 : std_logic_vector(2 downto 0) := "011";
signal pr_st,nxt_st : std_logic_vector(2 downto 0);
thank you very much for your time and any guidance,
best regards,
mirza
I have a doubt about declaring the type for state variables. normall its declared as :
type sm is (sate1, stae2, stae3...);
signal pr_st, nxt_st: sm;
what difference it will make in synthesis or function of circuit if its done like this way
constant sate1 : std_logic_vector(2 downto 0) := "000";
constant state2 : std_logic_vector(2 downto 0) := "001";
constant state3 : std_logic_vector(2 downto 0) := "011";
constant state4 : std_logic_vector(2 downto 0) := "011";
signal pr_st,nxt_st : std_logic_vector(2 downto 0);
thank you very much for your time and any guidance,
best regards,
mirza