How to add assertions in the simvision waveform viewer

shm_probe

I have written assertion to verify certain timing protocol. I am using cadence's simvision tool for waveform analysis. But I don't know how to add the assertions in the simvision waveform viewer. Is there any setting for this?

Please help me.
Thanks in advance.

cadence simvision

dipakg said:

I have written assertion to verify certain timing protocol. I am using cadence's simvision tool for waveform analysis. But I don't know how to add the assertions in the simvision waveform viewer. Is there any setting for this?

Please help me.
Thanks in advance.

Click to expand...

No special switches/flags needed, assertions are browseable/viewable just like regular nets/signals. Are you using mmediate or concurrent assertions?


When you compile the testbench and probe signals in simvision, the object 'my_assertion1' is the assertion-object. In the design-browser, it will show up as RED

shm_probe ac

Hi boardlanguage,

I tried the following thing in my code(assert_ack.sv):
###############################################
module hahahahahaha;

my_assertion1 : assert property ( @(posedge clk) disable iff ( !rstn )
req |-> ##1 ack; // expect ACK signal 1-cycle after REQ
);


initial
begin
$dumpvars(1,my_assertion1);
end
endmodule

###############################################

Then I ran assert_ack.sv by questa:

> qverilog assert_ack.sv

and to observe the waveform on simvision:
> simvision &

But it only showing the name of the signal not the status of the signal in the simvision window.

Can you tell me where is my mistake or I did anything wrong?
Thanks.

simvision waveform

I'm confused, are you using Simvision (Cadence IUS), or Questasim (Mentor Modelsim)?

Each product has its own debug-browser and user-interface. I only know how to look at assertions in Cadence Simvision. I've never used Questasim before.

$shm_probe

Hi boardlanguage,

See I am using Questa for simulation. The qverilog command compiles (vlog), optimizes (vopt), and simulates (vsim) Verilog and SystemVerilog designs in a single step. It combines the compile, elaborate, and simulate phases together, as some users may be accustomed to doing with NC-Sim.

And then Simvision as a waveform analysis.

Regards,
Dipak.

simvision assertion browser

Wow, I never thought to mix two competing products like that.

I don't know how to answer your question. NCSIM's integrated TRN (signalscan-trace) dumper records assertion-information -- in the Simvision waveform viewer, you can browse assertions and view their counts (failed, completed, active) as regular waveforms.

I don't know whether Questasim has this ability. Also, how are you reading the simulation waveform file? Did you dump out a VCD or extended-VCD file, a TRN file, or Modelsim's native .WLF file? From what I recall, simvision only reads TRN files directly -- VCD-files can be imported (converted on the fly).

ncsim vcd dumpports

I dump VCD files and then simvision converts it into .TRN file.

--Dipak

shm_probe ac as

I can't think of anything else.

In questasim's integrated waveform-viewer, can you browse/view the assertions? If the answer is yes, then I suspect the issue is with the VCD-file not being able to store assertion-information.

When I run simulation in Cadence IUS 6.2 (irun/ncsim), then open the *.trn file in Simvision, I can see every assertion listed as a hierarchical signal.

It looks sort of like this:

**broken link removed**

(Skip ahead to 3/4 toward the end of the movie.) The count, #failed, #passed shows up.

simvision dump file

Hi boardlanguage,

Thanks for your kind support....

Now, I am running the verilog code and assertion(SVA) using Cadence IUS 6.11 ncsim and then for waveform I am using Simvision... The similar problem I am facing in this case also.

Let me know if you are aware of this thing.

Regards,
Dipak

simvision $shm_probe

Is your simulation still dumping to VCD? (I.e., are you using the $dumpports or $dumpfile system-task to handle the dump-activity?) If you are, then that could be the problem.

All modern simulators (Modelsim, VCS, Incisive) have their own proprietary wavedump format. This is not only the fastest (in terms of runtime), but also the most complete tracedump you can get.

For Cadence/Incisive, there are several different ways to dump traces to a *.trn file:

1) From the Verilog-file
$shm_open( "waves.shm",,,0 );
// dump trace to subdir './waves.shm)
// ,,,0 disable compression (slows down the simulator)

$shm_probe( "AC", toplevel_tb );
// "AC" : all signals in current scope, AND all signals beneath current scope
// toplevel_tb : name of the toplevel module (change this as needed)

2) from the tcl-interpreter:
probe ...;
// Sorry, i don't remember the command. It's in the cdnshelp documentation.

Finally, whatever method you choose, there is one extra step: tell the simulator to allow read-access to internal signals (otherwise the integrated *.TRN dumper can't see the design hierarchy.)
Add the command-line option +ncaccess+rwc

Example:

(It's either +ncaccess+ or +access+, I forget which.)

irun assertion switches

Hi boardlanguage,

I am very thankful to you. Aah it worked finally...
I tried the $shm_open and $shm_probe....
Thank you very much.

--Dipak