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    How to divide 32768hz clock signal to 1hz clock signal?

    how i can divide 32768hz clock signal to 1hz clock signal? i have written the code.but it is diffcult to see the simulation result.who can give me a good advice ,thank you.

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  2. #2
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    Re: PLEASE HELP!!!

    Hi,
    Did you use VHDL or C .....???



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    Re: PLEASE HELP!!!

    hi
    i use verilog HDL.



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    Re: PLEASE HELP!!!

    Hi,

    You can make a counter of modulus (count) 32768 to get 1Hz clock. This is the basic way to devide the frequency through HDL code.

    Let us see if any one suggest a new method for clock devision.


    Regards,
    Vishwa



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    Re: PLEASE HELP!!!

    hi,
    what you said is right,but how can i see the whole simulation waveform?
    [code]
    module DIVIDER(clkin,reset,clkout,count);
    input clkin,reset;
    output clkout,count;
    reg clkout;
    reg [15:0] count;
    always @(posedge clkin)
    begin
    if (reset)
    begin
    count<=0;
    clkout<=clkout;
    end else
    begin
    if(count==32767)
    begin
    count<=0;
    clkout<=clkout;
    end
    else if(count<32767)
    begin
    count<=count+1;
    clkout<=count[15];
    end
    end
    end
    endmodule
    this is my code.i can not get the simulation waveform clearly.



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    PLEASE HELP!!!

    Yes use a counter and one assertion when the counter reaches 32767 the program prints the assertion.



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    PLEASE HELP!!!

    I do not understand why you use if(count==... and if(count<.. - the counter will turn on 32768 pulse.



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    Re: PLEASE HELP!!!

    i use it to make the counter to zero once counter==0,if not,it increase itself by one. do have a better idea?



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    PLEASE HELP!!!

    If you are having difficulty operating the simulator, please say which simulator you are using, and clarify the problem.

    If you simply want to divide 32768 Hz down to a 1 Hz square wave, then use a 15-bit counter and output the most significant bit. For example:
    Code:
    module top (clk, out);
      input         clk;
      reg    [14:0] count = 0;
      output        out;
    
      assign out = count[14];
    
      always @ (posedge clk)
        count <= count + 1;
    endmodule
    Of if you want a single pulse instead of a square wave:
    Code:
    module top (clk, out);
      input         clk;
      reg    [14:0] count = 0;
      output reg    out = 0;
    
      always @ (posedge clk) begin
        count <= count + 1;
        out <= count == 32767;
      end
    endmodule



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    PLEASE HELP!!!

    Well, the ech047 said what I had to say.
    I don't use Verilog, but in VHDL it looks quite the same.



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    PLEASE HELP!!!

    if you're using VHDL use this piece of software from another topic to generate VHDL code you need https://www.edaboard.com/viewtopic.p...ng+fixed+clock



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    Re: PLEASE HELP!!!

    thank you every guys very much!!!



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  13. #13
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    Re: PLEASE HELP!!!

    Quote Originally Posted by dmk
    Well, the ech047 said what I had to say.
    I don't use Verilog, but in VHDL it looks quite the same.
    hi,
    yes,you said is right.i did not get it.
    thank you.



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    PLEASE HELP!!!

    Hi higildedzest,
    Synthesize ur code and see the hardware formed each time..Its the best way to design optimized circuits.



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