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  1. #1
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    AWGN channel model in Verilog

    I'm interested if anyone did this in verilog. I have some C, C++ and Matlab versions bat interested to obtain HDL version.

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  2. #2
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    AWGN channel model in Verilog

    I‘m need it too。can u analyze code as following:

    ************************************************** *****************************/
    /************************************************** *****************************
    The module generates noise,using downlink m-sequences.
    The x sequence is constructed using the primitive polynomial
    1 + x( 7 ) + x( 18 ).
    The y sequence is constructed using the ploynomial
    1 + x( 5 ) + x( 7 ) + x( 10 ) + x( 18 ).

    x is iniatialized with x( 0 ) = x( 1 ) = x( 2 ) ... = x( 17 ) = 0,
    recursive definition
    x( i+ 18 ) = x( i + 7 ) + x( i ) modulo 2.

    y is iniatialized with y( 0 ) = y( 1 ) = y( 2 ) ... = y( 17 ) = 1.
    recursive definition
    y( i + 18 ) = y( i + 10 ) + y( i+ 7 ) + y( i+ 5 ) + y( i ) modulo 2.

    Noise output is z( i ) = x( i ) + y( i ) modulo 2.

    ************************************************** *****************************/

    module GEN_NOISE (
    // input data
    Clk16,
    Reset,
    Node_sync,
    Channel_noise,

    // output data
    Noise_data
    )/* synthesis syn_hier = "hard" */;



    input Clk16;
    input Reset;
    input Node_sync;
    input [9:0] Channel_noise;

    // output data
    output [9:0] Noise_data;

    reg [9:0] Noise_data;
    reg Noise_start;
    reg [ 17:0 ] Xseq;
    reg [ 17:0 ] Yseq;

    wire [ 1:0 ] Xshift;
    wire [ 2:0 ] Yshift;
    wire [ 1:0 ] Noise_out;
    wire [9:0] N_NOISE_ENG;

    // module begin.

    //************************************************** ****************************
    ////////////////////////////////////////////////////////////////////////////////
    // Wait node synchronous signal.

    always @( posedge Clk16 or posedge Reset )
    begin
    if( Reset == 1'b1 )
    Noise_start <= 1'b0;
    else
    if( Node_sync == 1'b1 )
    Noise_start <= 1'b1;
    else;
    end

    ////////////////////////////////////////////////////////////////////////////////
    //************************************************** ****************************

    //************************************************** ****************************
    ////////////////////////////////////////////////////////////////////////////////
    // Generate x and y sequence.

    assign Xshift = Xseq[ 7 ] + Xseq[ 0 ];

    always @( posedge Clk16 or posedge Reset )
    begin
    if( Reset == 1'b1 )
    Xseq <= 18'b0;
    else
    if( Noise_start == 1'b1 )
    begin
    Xseq[ 16:0 ] <= Xseq[ 17:1 ];
    Xseq[ 17 ] <= Xshift[ 0 ];
    end
    else;
    end

    ////////////////////////////////////////////////////////////////////////////////

    assign Yshift = Yseq[ 10 ] + Yseq[ 7 ] + Yseq[ 5 ] + Yseq[ 0 ];

    always @( posedge Clk16 or posedge Reset )
    begin
    if( Reset == 1'b1 )
    Yseq <= 18'h3ffff;
    else
    if( Noise_start == 1'b1 )
    begin
    Yseq[ 16:0 ] <= Yseq[ 17:1 ];
    Yseq[ 17 ] <= Yshift[ 0 ];
    end
    else;
    end

    ////////////////////////////////////////////////////////////////////////////////
    //************************************************** ****************************
    // Generate noise data.

    assign Noise_out = Xseq[ 0 ] + Yseq[ 0 ];

    assign N_NOISE_ENG = ( ~ Channel_noise ) + 1 ;

    always @( posedge Clk16 or posedge Reset )
    begin
    if( Reset == 1'b1 )
    Noise_data <= 11'b0;
    else
    if( Noise_start == 1'b1 )
    if ( Noise_out[ 0 ] == 1'b1 )
    Noise_data <= N_NOISE_ENG;
    else
    Noise_data <= Channel_noise;
    else
    ;
    end


    ////////////////////////////////////////////////////////////////////////////////

    endmodule // End GEN_NOISE


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