wasp
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:?:
How it is possible to receive the set delay of a signal on output FPGA?
The project on Spartan. I use ISE4.1 + Synplify (VHDL).
Or how it is possible to use attribute "X" in VHDL? Whether is such constraints which forbid to delete logic at stage Map?
How it is possible to receive the set delay of a signal on output FPGA?
The project on Spartan. I use ISE4.1 + Synplify (VHDL).
Or how it is possible to use attribute "X" in VHDL? Whether is such constraints which forbid to delete logic at stage Map?