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    What are the different FPGA file formats?

    what are the different file formats used with FPGAs
    someone told me the companies keep them as secret.

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    fpga file

    Dear cherin
    i think the file formats depend on the software and the language that u are using.for example if u use VHDL the file format might be ".vhd"



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    fpga .bit .bin file

    Design input file are generally readable (VHDL or Verilog logic definition, pin mapping, timing constraints, testbenches). Sometimes design units (IP cores) are distributed as encrypted files, only readable by the design compiler that knows a secret key.

    The design output, specially the bitstream used for FPGA configuration is generally not readable and it's meaning is undocumented. Also the exact FPGA hardware structure, e. g. the design of configuration resources controlled by the said bitstream is actually kept as a secret. Intermediate results as the compiled netlist are usually available as text files for simulation with third party tools.



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    fpga bit to bin file

    I am planning to build an FPGA programer
    So i need to extract the fusebit information from 'an output file' and send it in the right sequence to the fpga.

    U mentioned that the bitstream used for fpga configuration is not readable and that the format is undocumented.

    could u tell me the file extension? [like .jed for some CPLDs]



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    bin and bit file xilinx fpga

    Hi cherin, If you are referring to Xilinx, the bitstream filenames are *.bit or *.bin. They are nearly identical. The default *.bit file simply adds a small header. You can transmit the file contents directly to an FPGA via JTAG, or serial, or parallel techniques. There's no file decoding required. For more info, see the "Configuration User Guide" for your particular FPGA type.

    If you wish to understand the data in the *.bit or *.bin file, then that's Xilinx proprietary info.


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    fpga file extension

    Not readable was related to the meaning of the data. You can use it for configuration as documented by the manufacturer.

    FPGA usually have a volatile SRAM based configuration and don't utilize fuse bits respectively flash memory. For these, a FPGA programmer would be of limited use.

    Devices with nonvolatile configuration, e. g. all CPLD and some FPGA, generally allow JTAG programming in production by third party tools with documented methods, mostly according to IEEE 1352 standard.


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    fpga downlaod file format

    Hallo FvM,
    could please explain what is meant by "the exact FPGA hardware structure, e. g. the design of configuration resources controlled by the said bitstream", precisely "configuration resources".

    also it will be greatful if you mentioned the extension for the following files:
    systemverilog
    pin mapping,
    timing constraints,
    testbenches,
    IP cores

    The design output

    Intermediate results



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    *.bit file format xilinx

    When you program a simple logic circuit to a FPGA, e. g. two input pins are routed to a logic cell, the result is routed to an output pin, a lot of configuration resources is involved. Sometimes these resources are symbolized as switches in a functional FPGA schematic, but mostly, their operation isn't mentionend explicitely. All these configuration resources are programmed by the configuration bitstream, but you won't find manucturers literature that explains how this configuration exactly works (respectively I didn't see it yet). How do you imagine a connection setup in a FPGA? Do you have wires connected by three-state buffers as in a computer backplane (probably not), or rather a chain of incremental connections with multiplexers in-between (more likely).



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    ieee1352

    muhammad_ali, If you are referring to Xilinx ISE tools, then some of your answers about filename extensions can be found in Appendix A of the "Development System Reference Guide":
    http://toolbox.xilinx.com/docsan/xil...cs/dev/dev.pdf



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    xilinx jprogram

    http://toolbox.xilinx.com/docsan/xil...cs/dev/dev.pdf

    In appendix A of the above pdf, it is mentioned that we have to download the contents of the .jed file to the FPGA.

    For .bit the description is " Download bitstream file for devices containing all of the configuration information from the NCD file"

    Nothing is mentioned about the .bin file

    This information looks like a contradiction to echo47's previous post

    Added after 49 minutes:

    Being more specific...

    If i restrict myself to only the spartan family of xilinx FPGAs, which file should i directly download to a JTAG programer that i am to make?



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    cpldfit jed

    Check Appendix A again. JED files are created by the CPLDfit utility which is for CPLDs, not FPGAs.

    It's true that Appendix A doesn't specifically say that bit files are for FPGA, and it neglects to mention bin files. Xilinx likes to scatter useful info throughout its documentation. See page 309 of the Development System Reference Guide for a little more info about bit and bin bitstream files.

    You can download either bit or bin files through JTAG directly to Spartan or other Xilinx FPGA devices. I've written a small JTAG utility that does exactly that, using a parallel port interface. (I wrote it for a company, so sorry I can't share it.) You will need to issue the correct JTAG commands so the FPGA will accept your bitstream data. The command sequence is described (but perhaps not thoroughly) in the Configuration User Guide for your FPGA type. To find the correct chapter, search the manual for the word JPROGRAM.

    Sometimes I use iMPACT to generate a SVF file (a sequence of JTAG commands and responses), and then study that file to better understand the sequence required by a particular FPGA operation. Your program could parse and execute a suitable SVF file to configure the FPGA.

    I prefer to use bin files, even though the FPGA will ignore the header at the beginning of the bit file.

    Do you mean Spartan, or Spartan-II, or Spartan-3?
    Here's the Spartan-3 Generation Configuration User Guide. The JTAG programming info begins in Chapter 9, page 187:
    http://www.xilinx.com/support/docume...ides/ug332.pdf


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