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Introductory materials about floorplanning

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tooh83

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hi , everyone

I want to learn floorplanning . can anyone give me a good introductory floorplanning material . thanx in advance
 

Re: floorplanning

Which tools do you want to use? Astro or SoC encounter? Maybe the following material is useful for you.
 

Re: floorplanning

Another material
 

Re: floorplanning

i need to know at first what is floorplanning ? how to floorplan ? floorplanning algorithms ? a step-by-step floorplanning example and plz in english
 

floorplanning

Hi, look at my posts in the following Floorplan discussion made some months ago...:
 
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Re: floorplanning

is it really necessary to learn about floorplanning??
in xilinx the place and route and floorplanning is done automatically by the tool right..
 

floorplanning

Tan, It depends on which world you use to work and design... Probably in the Digital world is not that critical to do a chip floorplan and you can rely on automatic tools for doing it, but as an Analog-Mixed Signal design engineer with more than 10 years of experience, an a lot of products in the market, I strongly recommend a good floorplan for any chip with a critical Analog part, even when it's a really minor chip's portion...

Within my group, I do not approve any step further in a design if a good floorplan is not defined first. It's a key first step for getting a good and functional part after silicon processing...
 

Re: floorplanning

WOW!!!...
Kudos to the explaination
That was a wonderful reply..thanks so much for your clear explaination..
so only in the analog world we need to do floorplannignseperately..
it is possible to do in the digital world as well or the tool automatically does that??

awaiting your reply..
 

Re: floorplanning

HI Tan,

It is not correct notoin that the Analog designs only require the correct floorplanning and for the digital designs the eda tools will take care of the floorplannig !!

Right Floorplannig in my view ::
1) Appropriate placement of the macros / memories in the Deisgn for the SOC that interacts with the internal design or the external world through the bond pads of the design
2) Shoud have Less congestion for the further steps
3) should reuiqre less wire length for routing with the placement of the macros in your design .

So ., even for a digital SOC , the floorplan step much needed for the optimized designs

suresh
 

Re: floorplanning

But how to do floorpalnning manually..
see i am design engineer i work with XILINX tool..
i write an application according to my needs and just click RUN ALL...
it does everything..

from your post i assume that floorplanning in XILINX does minimal work..to get maximum out of it we have to seperately do floorplanning..
if it is done so how to do it??
 

floorplanning

Actually, in FPGA domain, if U want to get a excellent result, U must manually floorplan, placement to get the best timing of the critical path or design.
Manually modify the physical design in FPGA is a very hard work, but it's very useful and must be.
Tool can not do any more things U want to get.

Added after 4 minutes:

Tan
In Soc and ASIC domain, floorplan means the major task in back-end. U must keep ultilization over than 90%. no conjection issue. no power drop issue.
Of course, it's relationship with cost. it's means the money income.
 

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