yuguo
Newbie level 4
LVS for digital design
I am designing a mixed-signal circuit
the digital part is implemented using Verilog, synthesized with DC and the backend is done with SOC encounter, now the problem is how to do LVS
The standard cell vender gives us a CDL file for LVS, in which it defines the sizes of transistors and their connections, but using simplified PMOS/NMOS model files (can't work with Spectre/SPICE, just show the transistor sizes).
I have the GDS file and also the verilog source code, is there anyone know how to utilize the CDL file provided as "LVS netlist" for LVS? Btw, I am using Calibre.
Thanks and any sugguestion is appreicated.
I am designing a mixed-signal circuit
the digital part is implemented using Verilog, synthesized with DC and the backend is done with SOC encounter, now the problem is how to do LVS
The standard cell vender gives us a CDL file for LVS, in which it defines the sizes of transistors and their connections, but using simplified PMOS/NMOS model files (can't work with Spectre/SPICE, just show the transistor sizes).
I have the GDS file and also the verilog source code, is there anyone know how to utilize the CDL file provided as "LVS netlist" for LVS? Btw, I am using Calibre.
Thanks and any sugguestion is appreicated.