Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

How to do LVS for digital part of mixed-signal circuit ?

Status
Not open for further replies.

yuguo

Newbie level 4
Joined
Feb 24, 2005
Messages
6
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,337
LVS for digital design

I am designing a mixed-signal circuit
the digital part is implemented using Verilog, synthesized with DC and the backend is done with SOC encounter, now the problem is how to do LVS

The standard cell vender gives us a CDL file for LVS, in which it defines the sizes of transistors and their connections, but using simplified PMOS/NMOS model files (can't work with Spectre/SPICE, just show the transistor sizes).
I have the GDS file and also the verilog source code, is there anyone know how to utilize the CDL file provided as "LVS netlist" for LVS? Btw, I am using Calibre.

Thanks and any sugguestion is appreicated.
 

Re: LVS for digital design

It seems that you need to you calibre to convert verilog netlist to CDL files and write a file that includes digital netlist and analog netlist. Then you can run LVS.
 

Re: LVS for digital design

Thanks for the kind help~~~

zhongdg said:
It seems that you need to you calibre to convert verilog netlist to CDL files and write a file that includes digital netlist and analog netlist. Then you can run LVS.
 

LVS for digital design

I guess zhongdg is right. See the following page.

**broken link removed**


Hope this helps
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top