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Why do we avoid latches in the design?

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alam.tauqueer

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Why we avoid latches in the design, even if they provide only cell delay.
Is there any time related issues??

regards,
Tauqueer
 

Re: Latches in th design

Whenever latch is enabled it will pass watever is there on its D inputs to Q output. If suppose any glitch is coming on D and latched is enabled it will pass it to q. Glitch always create problem u would be knowing this.

Latches are fast,consumes less power, less area than Flops but Glitches can also come along with this advantages.Thats why we for flops.
 

Re: Latches in th design

Also Latches are not DFT friendly... It is very difficult to perform Static timing analysis with latches in your design...
 

Latches in th design

Can u please explain me like
Why it is very difficult to perform STA with latches in the design....

Regards,
Tauqueer
 

Re: Latches in th design

latch is not good ,since STA is based on posedge of clk to do timing check and latch is level sensitive. also DFT need to do some special step to tackle this latch!
 

Latches in th design

can you please explain me what are those special step to tackle the latches in the DFT .
It would be great help for me to understand the problem.

Regards,
Tauqueer
 

Re: Latches in th design

Please tell me how does a flip-flop not allow glitches but a latch does?
 

Re: Latches in th design

HI

Latches will allow the data at the input to reflect at the output till the entire time the Latch is enabled , ie when it is enabled it is called to be transparent ie the output follows the input thus if a glitch appears it will be reflected at the output

but the case with FF is not so , the output follows the input only at the edge of the clock whether positive or negative .

thus any glitch appearing at the input will not be transfered to the output unless the clock edge appears

hope this has clarified your doubt
 

Re: Latches in th design

Tauqueer,
If your design is complety latch based design( usuallly IBM designs) then you can use the LSSD scan else normal scan FF based desing, you can make the latches as transparent during testmode. For example clock gating cells has the latch, you ORed with testmode signal.
non transparent latches are modeled as TIEX by the ATPG tool. So the coverage drops.
~C Santhosh Kumar
 

Re: Latches in th design

Taqueer,

Before enable of the Latch place a 2X1 mux with sel and one pin tied with test mode signal (OR gate with testmode and actual enable signal). Intent is to make Latch always on while doing DFT coverage..
 

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