about ASIC design flow for 0.13um logic?

design flow 0.13

I'm a beginer in ASIC design . can anyone tell me about ASIC design flow for 0.13um logic. what tools used?
I know little from RTL to gdsII

synthesis --- synopsys DC
prelayout STA ----- PrimeTime
P&R -----Astro or SOC encounter
verification ---- calibre or hecules or Assure
postlayout STA ----PrimeTime

how about DFT? in synthesis ? what tool? DFT compiler?
how about Power analysis or SI ?

0.13um synthesis placement timing

For Power analysis we can use Vstorm given by cadence....or Prime Power by Synopsis

For Signal integrity we can use CELTIC by cadence...or PrimeSI by Synopsis

For std cell design we can use Virtuso layout editor..or Magic or Tanner L-edit,Labview,Microwind

To know how many stuck at faults are there in ur design we use DFT visualizer..

For Physical verification we can use Caliber by mentorgraphics..or Assura by Cadence..

For STA we can use ETS By cadence which is the latest one in the market..or Prime time by Synopsis..

For P&R we can use SOC encounter by cadence and Astro by Synopsis..

For synthesis we can use RTL compiler by cadence or DC(design compiler) by synopsis

Added after 2 minutes:

I will tell u the cadence flow..

Synthesis
PreplacementOptimization
Floorplan
Powerplan
Placement
Prects
CTS
postCTS
Nanoroute
Vstorm/Celtic
Timing Signoff

signal integrity 0.13um

verilog coding-> synthesis-> dft scan insert->formal( rtl2net)-> P&R-> formal)net2net)-> STA->GLS->timing closure

asic design flow

this is good tool for drawing layout . there are also alot of example