Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Verification Questions in Interviews

Status
Not open for further replies.

bismillah

Member level 1
Joined
Jul 18, 2005
Messages
40
Helped
1
Reputation
0
Reaction score
0
Trophy points
1,286
Location
Earth
Activity points
1,642
Hi,

I will be facing interview for verification engineer job with a client. Can anybody please tell me what questions to expect and what are the answers.

Thanks in advance
 

u can be asked about formal verification, verification enviornment, checkerboard methodology, bfm..
 

bismillah said:
Hi,

I will be facing interview for verification engineer job with a client. Can anybody please tell me what questions to expect and what are the answers.

Thanks in advance

Lot of Interview question can be found Here:

https://vlsifaq.blogspot.com/
 

Thanks,
Is there a way one can obtain some hands on training in verification with HVL like Vera, systems verilog, system c, with self learning tutorials?
 

Read the things about Code Coverage , there is paper from Mentor Ghraphics AVM " Adavance Verification methodologies " that is really useful people for newbie's and learners .

shobhitkapoor[at]gmail[dot]com

Added after 1 minutes:

Yes posible with System Verilog and SystemC find a demo modelsim from mentor ghraphics and download it on ure system ...find a tutorial of System Verilog ( Say www.asic-world.com ) and Start the desired Task
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top