Internal bus implemented inside Fpga.

fpga internal bus

I read material says that bus can be implemented in Fpga using multiplexer. Is there anyone kindly enough to explain me how it works ? and are there any resources ,say,tri-state logic gates, inside Fpga? or tri-state gates only available when using I/O pins ?

Any input is appreciated!

thanks in advance!

fpga bus

There are lots of resources inside and FPGA. The specific types and amounts available are dependent on the specific part.

To answer your question about using a mux to implement a bus; if you have to ask that question I would ask you about your HDL experience. If you need a data bus either specify it in the entity or as a internal signal. The fact that you would use a mux would be to control what is being sent down the bus based on the inputs to the mux.

E

fpga internal tristate

Yes, FPGAs have internal tristate buffers with which to build buses. You do not have to really worry about this. The FPGA tools take care of inferring these buffers when they are needed.

The typical Verilog syntax is:

assign reg_rdd = (val_oe || stk_oe ) ? rddata: 32'bz ;

In this example if either "val_oe" or "stk_oe" are '1' then reg_rdd is driven by rddata. Otherwise, reg_rdd is floated to a high z state.

The key is the conditional operator "?".

Let the FPGA compiler worry about how to implement it. The compiler may use the dedicated tri-state buffers, or it may combine functions into LUTs to reduce the demand on these buffers. It all depends on your design.

internal bus fpga

nxtech,thanks for your quick reply!

i have the experiment of writing Hdl for controlling some Peripheral, but i am wondering how a bus is implemented in fpga. take cyclone fpga for example, i get a chip EP1c3, and i want to know whether the chip has some tri-state gates inside it.i also know that the chip is support NIOS, and how its bus is implemented ? using tri-state gates or mux ?

thanks again!

Added after 8 minutes:

banjo, you clear my doubt!
thanks very much!
too quick a reply really makes me surprise! i think many people visit this forum!
will the datasheet of special fpga tell us some tri-state gates in fpga ? or they just don't tell and we use it as it exists ?

fpga internal tristates

The datasheets used to list this feature, but it usually deeply buried. The reason is not many people care about the number of buffers as long as they never run out! In the Xilinx parts, these buffers and distributed within the fabric of the CLBs. On a regular grid, these elements will appear among the CLBs or Slices. With the Xilinx tool, you can always open FPGA Editor, locate a few of these blocks and quickly estimate the total since the placement pattern is fixed.

I would suggest coding up a quick test case and placing it in your part. Look at the reports, if you are critically low on T-Bufs, it should tell you or fail. After that, you just have to trust the tools to find a way to implement your logic. Usually, they are very good. I cannot remember having a fitting problem with the available T-Bufs for internal busses.

If you are still concerned, contact your local sales rep. They can query the factory and get an exact number for you.

fpga tri-state

My understanding is, that all FPGA internal signal switching is achieved through multiplexers respectively LUTs. If you define three-state busses, the compiler translate it to multiplexers. With most FPGA tools (I guess also with Xilinx), you have technolgy map viewers, that show which FPGA resources actually have been used for the defined logic.

Although I generally agree with the viewpoint that you should leave it to the compiler to find a solution for your logic, it may be helpful to keep some restrictions of FPGA in mind when designing logic, e. g. the fact, that a three-state bus has to be resolved as point-to-point connection with multiplexers at each receiver. For that reason, busses in soft processors are usually designed unidirectional with separated read and write data lines that can be operated in parallel.

fpga three state bus

thanks for sharing ideas with me,banjo and FvM! you do help me a lot!
Now i get the idea of an internal bus, when coding , i don't fear it any more,just see how the compiler tell me what it has done!

what is inside fpga

@fvm,
for soft processor, is it expensive to use tristate buffers (and better to use two seperate buses for In/Out).
what you say,

fpga internal busa

I think the compiler generates separate busses, or more exactly, point to point connections anyway. Designing separate busses from the beginning may achieve higher throughput, cause it may be operated full-duplex in some situations.

And it's important to check the synthesis output, cause different compilers may give different results.

internal tri state fpga

I am also facing the same problem. I wish to design an internal Bus. right now i m in concept phase.

I have one bus controller and 32 sub systems. bus contoller will be reading or writting data to any of the 32 sub systems at a time. there will be a uni-directional shared data bus.my estimate is that i would require 16 * 32 = 512 BUFT resources in spartan 3S1000 !

i want to know would it be a gud design that would be using 512 BUFT resources to implement this simple BUS inside FPGA ? are there enough BUFT resoures i.e. more then 512 available?

internal tri-state inside xilinx

The Spartan 3 does not have any internal BUFTs. Synthesis will convert BUFTs to MUXes, but only if the option is enabled.

If you have a 16-bit bus with 32 sources of data, you will need 16 of the 32-way MUXes.