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how do people doing logic synthesis give SDC to back end

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someone says PT gives it and someone says DC gives it?

also what i dont understand is how does it give the value of
set_clock_transition set_clock_uncertainty and set_clock_latency?

thanks in advance
 

PT and DC both support these commands. DC is normally used in synthesis. PT is normally used in time fix, timing closure.
PT has more delicate clock tune like these different style set_clock_*
DC can be simpler, since you can give more tight constraint in synthesis.

www.nandigits.com
Netlist Debug/ECO in GUI mode
 

DC is used for synthesis and its only for setup. so, if your DC constraints are only for setup; then you will have to define both setup and hold constraints for back-end. if input to DC is full constraints, then SDC from DC will do the job. back-end needs both setup and hold constraints, no matter whether dc/pt gives.

set_clock_transition : dont worry about this
set_clock_uncertainty : check your PLL jitter and set this to that value
set_clock_latency : This also does not matter much. so you can ignore this. But if u want to control the maximum clock tree insertion delay in back-end; you can provide this.
 

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