Guidelines for floor plan of block level and top level

Hello,

I want some guidelines in the floor plan of blocklevel and also toplevell

Floor plan

I never see a guideline about floor plan.
It's all based on experience.
One of my friends is good at this.

Re: Floor plan

why not ?

ex : guide line1 :Routing driven foorplan : Floor plan ur block in such away that it decreses the routing and indeed it saves space and also reduces the parasitic cap.

Expecting more

Floor plan

1 - Create a list of the blocks and bond pads to be used and estimate the area of them.
2 - (In mixed signal) identify the "noisy" blocks.
3 - estimate the total die area and draw a limit die size then insert the blocks estimated in #1 but take care of placing the "noisy" blocks as far a possible from sensitive analog blocks... The bondpads must be placed also right now, verifying they are in a correct place to be bonded out...
4 - Within the digital (or noisy) blocks place them in such a way that clock lines get the shortest path as possible at toplevel routing.
5 - Draw some lines for TOPLEVEL PWR and GND so you can define where future PWR and GDN buses will be (where all the blocks will be getting their supply).
6 - Save area for toplevel routing buses (areas where you'll be able to route lines for toplevel interconnect)

Etc, etc.

As you can see, most of the things are obvious and logical things... As posted before it has to do A LOT with experience and practice but following the above mentioned list you can make sure you'll be more than ok.

Floor plan

What is the floor planning flow?
How can we place the blocks in core area (on what basis), how can we place the pads (power pads & Signal pads)?

expecting more information.

Floor plan

1 - BONDING PADS: The pads are one of the very first things to be placed (at least their relative position between each other) and that preliminar location is based on PACKAGE PINOUT. At the very beginning of your project you have to make sure that you'll be able to bond your chip once is finished...

2- Main block location reasons were already included in the former post:
a - Separate as much as possible digital (noisy) blocks from analog ones.
b- ONce the previous is done, place the blocks in such a way the interconnection is minimized.
c- Put as centered as possible the device you know as the biggest power dissipator

Re: Floor plan

We can say guidelines are the things that would help the design to work but not 100% the case. Here are some.
* As much as possible don't put sensitive blocks to location of high stress gradient.
* Consider the signal flow.
* There are blocks that must be placed side by side.

try to read layout books.

Re: Floor plan

To add to the above points,

The IR drop of Signals connectting to the PAD should be minimum. So those blocks that have the signals connectiong to pads are placed close to the PAD.

Re: Floor plan

layoutmaster said:

c- Put as centered as possible the device you know as the biggest power dissipator

Click to expand...

Can you elaborate more on point c.

Regards,
Sandeep

Floor plan

The ideal situation will be to center it, but it's not a must...

The idea behind that is to have an uniform thermal gradient (isothermal lines) across the chip in order to minimize thermal effects on very sensitive analog circuits.

That's why I say it's not a must. The important thing would be to know where this component is placed in order to be aware of it and place the sensitive components and circuits according to it in the rest of the chip. Hope this is clear now.

Re: Floor plan

blocks are usually placed at the center because it has the least stress gradient.

there are two types of chip design wrt to pad:

pad-limited and core-limited.

Re: Floor plan

Reaaly speking , it is much preferrable to place the most sensitive block say pga or else a sigma delta modulator in the centre of the chip as it is much free from stress gradients.
And by placing the most disspatory powe device in the centre of the block is the most dangerous thing to do.Power devices are always preferrable to place only in the corners of the die.

Floor plan

The floorplan varies significantly depending if it is a CELL, MODULE, CHIP.
CELL floorplan is tightly squeezed and lot of emphasis is given on area as this might be instantiated millions of times. Digital cells like AND, NOR ...
MODULE agian consists of two types : With IO and without IO ie Complex and Megamodule
CHIP has two types : IO limited or core limited.