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  1. #1
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    parallel patterns and the serial patterns

    i am confused about the parallel patterns and the serial patterns generated by the fastscan. do this two patterns have the same effect to the test coverage and the defult coverage?that is to sa,both types of patterns can match the test coverage requirement? can anybody tell the difference of this two type paterns?

    another question is when i generated the stuck-at patterns,then i generated the at-speed patterns,how do i get the summary of this two test coverage result.

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  2. #2
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    Re: parallel patterns and the serial patterns

    Hi ,

    Q1.

    The test coverage is ready even before we write the patterns. So the format of the patterns has nothing to do with the coverage. The ATPG tool will have a pattern format internal to its memory which is actually giving you the test coverage.

    Now, at the end of the ATPG we give the command to write out these patterns. There are different formats in which we can write these patterns. WGL,VHDL, STIL, EDIF etc... The internal pattern set of the tool is then written in your required format.

    These can further be written in serial or parallel format. So what is the difference between parallel and serial?

    First thing, you cannot write in parallel in all the formats. Parallel is generally for Verilog or formats which can be simulated on a simulator like VCS, modelsim etc.

    What this means is that the parallel format is only for the simulation purpose. It is not used on the ATE. It is the serial patterns which are applied on the ATE.

    In parallel patterns we use the concept of "force/release". The scan pin of the Flops are directly forced rather than serially loaded. With this you can load your chain with just a single shift clock. This save a considerable amount of simulation time Let's say the length of your chain is 5000 then in serial mode it will require 5000 clock pulses to load this chain but in parallel mode, just one pulse will load all the 5000 flops. The value to be force on the pin comes from the pattern set.

    On ATE it is not possible to access the internal pins of the scan flops. All the load_unload has to be done from the top of the chip only.

    Q2. Are you looking for a combined coverage?

    This is not possible as these two are different fault models.

    -cheers
    vlsi_eda_guy



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  3. #3
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    Re: parallel patterns and the serial patterns

    nice answers vlsi_eda_guy......



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