What does memory inference mean ?

Hello

Is there anybody that can explain to me what exactly mean "memory inference". I didn't find any definition of what Ram inferring can be. Everybody seems to be concern about latch being infer and it really dangerous to have this kind of warning in your code. So I would like to know why I should worried about that and which coding methodology I should avoid to get rid of that???

thx

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array inferring hdl

Memory inference in HDL programming isn't anything you have to fear. It's basically a feature of HDL compilers to generate structural elements without an explicite declaration. The said "latch inference", although appearing in warning messages sometimes, is a similar process.

Assume a variable (or constant) array defined in VHDL or Verilog.


This variable definition is candidate for memory inference, but it also could be, that a large array of individual registers is synthesized. Most FPGA families have embedded RAM , and the synthesis tool should prefer RAM for variable storage, cause 2048 registers can be saved this way. But RAM can only be used, if the memory is accessed sequentially, one address at a time (could be two with dual port RAM, but it's inference may be unsupported by the compiler).

The synchronous nature of RAM sets additional constraints on it's usage. If all requirements are met, the synthesis tool will infer memory from the code by default, but you may block this by additional synthesis attributes. Otherwise it will use registers. HDL compiler handbooks usually discuss in detail the requirements for memory inference, the same with other structural elements as flip-flops, latches or multipliers

inferring RAM

The HDL synthesis tool recognizes (infers) familiar operations in your HDL code, and translates them into hardware entities such as counters, RAMs, flip-flops, gates, latches, shift-registers, state machines, adders, etc.

Inference is usually a good thing, a big time-saver. However, if you write careless HDL code, the synthesis tool may infer something different than what you intended. It can't read your mind, it only reads what you wrote.

Your synthesis tool users manual should explain how to write HDL code that helps the synthesis tool correctly infer various hardware features such as an FPGA Block RAM. For example, the Xilinx XST User Guide chapter "HDL Coding Techniques".

Re: inferring RAM

Thx

it's exactly what I wanted to understand

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