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Can we automatically translate schematic(or Verilog file ) to layout in Cadence?

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anhtuan

anhtuan

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Hi everyone!

I have some question about Virtuoso Cadence Software .

First, can we tranlate automatic from Schematic to Layout???
Second, can we translate automatic from Verilog file to Layout (like in Digital design
by Synopsys Sofware)??

If yes , what steps to do in Cadence ??
Thanks for your help!!!
 

Cadence Question!!!

None of them.
But gate-level verilog netlist can be place-and-routed in Cadence's other tools -- not fully automatically.
 

Re: Cadence Question!!!

What tool of Cadence for translate from gate netlist to layout??
 

Cadence Question!!!

First:
Virtuoso XL Layout Editor
second:
ENCOUNTER DIGITAL IC DESIGN PLATFORM

To do it, see Cadence documentation for details.
 

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