+ Post New Thread
Results 1 to 4 of 4

4th April 2008, 15:14 #1
 Join Date
 Mar 2008
 Posts
 12
 Helped
 0 / 0
 Points
 908
 Level
 6
Wrong output while trying to use module repeatedly..Help!
Code to find GCD...
I want the code to find GCD by foll. method..
gcd(a_in,b_in,a_out,b_out)
{ if((b_in==0)(b_in==1))
{ a_out = a_in;
b_out = b_in;
}
else
{ gcd(a_in,ain%b_in);//recursive function
}
}
This is the logic in C.....but in Verilog i dont know how to repeadtedly call the module modulus which fins a_in % b_in..
Below is my Verilog code,plese tell me where i'm wrong...
Code:module gcd(clk, start, a_in, b_in, a_out, b_out, done); input clk; input start; input [31:0] a_in; input [31:0] b_in; output reg [31:0] a_out = 0; output reg [31:0] b_out = 0; output reg done = 0; reg [3:0] cnt = 0; reg rst_in = 0; reg rst_start; integer a,b; wire [31:0] result; wire recv = 0; always@(posedge clk) begin if(start)begin a <= a_in; b <= b_in; cnt = 1; end else if(b==0  b==1) begin a_out <= a; b_out <= b; done <= 1'b1; cnt = 2; end else if(cnt == 1)begin rst_in<= 1; cnt = 2; end else if(recv == 1)begin a <= b; b <= mod_gcd.result; a_out <= 1; rst_in <= 0; cnt = 1; end end modulus mod_gcd(clk,start,rst_in,a,b,result,recv); endmodule
Code:module modulus(clk,start,rst,x,y,result,done); input clk; input start; input rst; input [31:0] x; input [31:0] y; output reg [31:0] result; output reg done = 0; integer rem,y1 ; always @ (posedge clk) begin if(start) begin rem <= x; y1 <= y; result <= rem; end else if(rst) begin if(rem < y) result <= rem; else rem <= rem  y1; done <= (rem < y); end end endmodule

Advertisement

8th April 2008, 11:45 #2
 Join Date
 Sep 2005
 Posts
 49
 Helped
 4 / 4
 Points
 2,451
 Level
 11
Re: Wrong output while trying to use module repeatedly..Help
Hi,
this peice of code i got from net...
Verilog algorithmic level model
module GCD_ALG;
parameter Width = 8;
reg [Width1:0] A_in, B_in, A, B, Y, Y_Ref;
reg [Width1:0] A_reg,B_reg,Swap;
parameter GCD_tests = 6;
integer N, M;
reg Passed, FailTime;
integer SimResults;
// Declare memory array for test data
// 
reg [Width1:1] AB_Y_Ref_Arr[1:GCD_tests*3];
//
// Model GCD algorithm
//
always @(A or B)
begin: GCD
A = A_in;
B = B_in;
if (A != 0 && B != 0)
while (B != 0)
while (A >= B) begin
A = A  B;
Swap = A;
A = B;
B = Swap;
end
else
A = 0;
Y = A;
end
1 members found this post helpful.

Advertisement

8th April 2008, 14:32 #3
 Join Date
 Dec 2006
 Posts
 84
 Helped
 6 / 6
 Points
 1,947
 Level
 10
Wrong output while trying to use module repeatedly..Help!
do not mix blocking and non blocking assignment usage on a single always block. i think this is a bad coding style and it is not recommended.
besides, RTL are concurrent programming and they are different compare to software coding style. so you cannot repeatedly "CALL" a single module. there no such thing like CALL in RTL.
you can instantiate the same module a few times with different instant's name but all this module will still execute concurrently.
1 members found this post helpful.

Advertisement

15th April 2008, 16:40 #4
 Join Date
 Mar 2008
 Posts
 12
 Helped
 0 / 0
 Points
 908
 Level
 6
Wrong output while trying to use module repeatedly..Help!
Thanks guys...i think i have to refresh a lot, before i can get into Verilog coding... it looks like simple coding, but works very differently... tell me some books i can refer so i can start to understand what to code, and what not...
+ Post New Thread
Please login