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Verilog - generate multiple interconnected modules

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segment[13:7] goes to 10's place of LED, segment[6:0] goes to 1's place.

Code: 
reg [13:0] segment;

always @ (sum1 or sum2 or ....) begin
  case({co, sum4, sum3, sum2, sum1})
     5'b00000: segment = 14'b0000000_0111111;
     5'b00001: segment = 14'b0000000_0000110;
     5'b00010: segment = 14'b0000000_1011011;
       .....
     5'b01010: segment = 14'b0000110_0111111;
     5'b01011: segment = 14'b0000110_0000110;
      ......
   endcase
end
 

hi...

This post was very useful...
I am a newbie to verilog. Is it possible to use "if statement " inside generate ??????? I tried to use , i am getting the error " Illegal reference to genvar i".

This is my code..

The variable "txrx" is output of another module.

genvar i;
assign i=0;
generate
if(i==txrx)
begin : prog
............................
...................
end
endgenerate
Click to expand...
 

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