Poly-Poly Capacitor Layout

poly capacitor

I need a big 10pF poly-poly capacitor. I saw some capacitor designs where the capacitor is broken down into several smaller ones, even with dummies and a guard ring, some kind of a centroid layout.

What's the motif of doing such a thing?

Do I need it for my poly capacitor?

cadence capacitor layout

if you look how large the poly cap will be it is not a good idea to make it as one big blob due to the processing.
Most of the extracted models for the devices has limited size so if you use something much bigger the model will not cover it. I believe that array of smaller caps with dummies arround them will give you better results.
Anyway with 10pF I would consider use of a MOS cap. due to the overall structure size.

poly-poly 2 capacitor

I agree with Teddy that, even when actually it's dependent from circuit needings and constrains (and probably it's not that critical the cap absolute value) always it's a good practice and a better layout technique to split the cap into smaller "unit cells" and place dummies arround them.

Also, and again it might be a circuit limitation, if possible it would be worth study which other cap alternatives has your process available...

poly poly cap analog

Usually MIM caps are laid out in small square units. The smallest practical perimeter-to-area ratio (and hence better matching - ΔC/C α P/A) is best achieved by making the capacitor square. Multiple square cap units laid out in a common centroid fashion will allow optimum matching.

mos cap and poly cap

The maximum size of the cap will be dictated by the design rules. The reason for such a rule is to prevent "dishing". Dishing occurs when the copper recedes below or protrudes above the level of the adjacent dielectric. Many fabs have process in place that prevent dishing and is thefore as not a big issue as it used to be.

Dishing and erosion, which together account for nearly 50 percent of yield losses n copper processing, are the most important effects to minimize in the copper chemical mechanical polishing (CMP) process. The mechanisms behind these
effects are complex, but semiconductor manufacturers are able to control and
reduce dishing and erosion through advanced metrology tools.

Dishing and Erosion Cause Yield Loss
and Affect Device Performance

Copper and the adjacent dielectric are removed from the wafer at different rates
during CMP, creating surface anomalies and a varying topography. Many factors,
including pattern geometry (e.g., line density), affect the removal rates and add to
these surface anomalies. The CMP process strives to achieve flat topography to improve
yield. Dishing and erosion are the two most costly surface anomalies that come about with copper CMP.

poly in layout

Teddy said:

if you look how large the poly cap will be it is not a good idea to make it as one big blob due to the processing.
Most of the extracted models for the devices has limited size so if you use something much bigger the model will not cover it. I believe that array of smaller caps with dummies arround them will give you better results.
Anyway with 10pF I would consider use of a MOS cap. due to the overall structure size.

Click to expand...

A MOS cap is not an option for me, since the supply voltage in my app is to low to provide linear mode of operation.

Where could I check what are the maximum device sizes for which the models are valid? Wouldn't my simulator (Cadence) send a message if I "oversize" it?

And most of all - what do I need the dummies for in the case when I need only one capacitance? I thought this is important only when one has two capacitors and wants to provide better matching between them.

poly capacitor capacitance

so professional
i am studying...
thank you

poly poly capacitor layout

malizevzek said:

I need a big 10pF poly-poly capacitor. I saw some capacitor designs where the capacitor is broken down into several smaller ones, even with dummies and a guard ring, some kind of a centroid layout.

What's the motif of doing such a thing?

Do I need it for my poly capacitor?

Click to expand...

It is up to your frequency level and requirement of the CAP.

Dummies is set for matching, and guard ring can reduce the noise.

Added after 2 minutes:

malizevzek said:

Teddy said:

if you look how large the poly cap will be it is not a good idea to make it as one big blob due to the processing.
Most of the extracted models for the devices has limited size so if you use something much bigger the model will not cover it. I believe that array of smaller caps with dummies arround them will give you better results.
Anyway with 10pF I would consider use of a MOS cap. due to the overall structure size.

Click to expand...

A MOS cap is not an option for me, since the supply voltage in my app is to low to provide linear mode of operation.

Where could I check what are the maximum device sizes for which the models are valid? Wouldn't my simulator (Cadence) send a message if I "oversize" it?

And most of all - what do I need the dummies for in the case when I need only one capacitance? I thought this is important only when one has two capacitors and wants to provide better matching between them.

Click to expand...

DRC rule will set the maximum size.
and why don't you use the P-cell?

capacitors for dummies

@jecyhale

P-Cell? I am relatively new to Cadence and its vocabulary. What I normally do when I want to use a Poly-cap, I invoke one PolyCap instance, set the dimensions and that's it. Did you mean that by mentioning P-Cell (Parametrized Cell)?

Anyway, my original question remains - do I need to "break" my big capacitance into several smaller and why...

design capacitor poly

ok ...If the design rules allow dont break up the capacitor. Surround the cap with a substrate tie.

If you break the rules split the cap into two.

We DONT have a limit for cap sizes and dont have issues.

Hope that clears it up!