Question on INL DNL measurement

hi friends,

i have designed a 12bit dual slope adc converter with clock speed of 1Ghz for which i want to measure inl and dnl. I have looked at the methods suggested on this forum like Histogram method based on sine wave signal or ramp signal. THe problem is each sample takes anywhere from 3 to 4hrs to complete. So if i do the histogram test it takes more than a month to complete the test. Is there any other way to measure the inl and nl of adc in a shorter time.

thanks.

Hi,
do you mean each conversion takes 3 to 4 hours!!!!!!!!!!! At what frequency are you operating friend????

Hi subharpe,

My digital block operates at frequency of 1Ghz.It takes total of 8192ns to compute full scale input voltage.

Yes it takes 3-4hrs for cadence ultrasim simulator to give out a conversion value.

Do you know of any other means to compute inl dnl

you may try some samples and test the difference
between the output and the input but it will not be accurate i may believe that the inl and dnl simulation
may take a day

I'm afraid that's the way it is. I faced the same problem some time ago. You may find tricks to estimate the inl or conversion error, but at the end of the day there's no way out. You need a number of samples per code and you need to simulate them, so, yes it takes ages.

The only thing you can do is to simulate conversion error instead of inl, that's just hitting once each code. That will give you a worst case limit for inl. For dnl is a nightmare too.

What I used to do is simulate 1 hit per code for the full range and then in the difficult parts (in my case, being pipeline was at 1/4 vref) simulate 20 hits per code.

The other thing that could be done is to simulate in parallel dividing the full range in parts and later on paste them all together. However, it seems difficult to join them all cleanly.

Good luck!