How to do Clock devider in FPGA!??

clock devider

Hi all,

I gonna use clock devided by 2 in my design. can anyone here tell me that:

1. should i just use a register to get clock-divided-by-2 or on-chip PLL!!??
2. what are the protential problem of using two clocks in a design when doing synthesis!!??

thank you in advance

regards,
always@smart

fpga output drive current

As far as I know, you can't do it in Altera APEX FPGA.

The clocks has to be used strictly on global clock lines.

what is clk ff stands for?

I think you can build a simple binary counter that increments with each clock then you take the output you need ; If you need clock/2 take the first output ; if you need clock /4 take the 2nd one and so on ..
here is a code for clock divider to divide by 16 , 32 , 64 ...


ibrary IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity clockdiv is
port(
clock: in std_logic; -- clock input
bitclk4: out std_logic; -- clock/16 (4*bit clock)
bitclk2: out std_logic; -- clock/32 (2*bit clock)
bitclk: out std_logic); -- clock/64 (bit clock)
end clockdiv;

architecture BEHAVIOUR of clockdiv is
signal q: std_logic_vector(5 downto 0):="000000";
begin

process(clock,q)
begin
if (clock'event and clock='1') then
q <= q+1;
end if;
bitclk4 <= q(3);
bitclk2 <= q(4);
bitclk <= q(5);
end process;

end BEHAVIOUR;


if you need clock/2 just take q(0)

for the check of multiple clocks ; I don't think it's synthizable... I think you should make your check on one clock only ...

24ma driving fpga pin capacitance

Hi all,

Thanks for help..let me explain a little bit more of my design

i'm targetting to use A!ter@ cycl0ne EP1C6, that have 2 internal PLL there.

Now I'm using two clocks in my design, clock and clock_div2, I'm planning to use the internal PLL to build the clock_div2 and also still consider the suggestion from Vonn(see above msg).

i'm more concern of the synthesis after the system has been synthesize, i'm not sure whether it will violate the setup-time or not, since clock_div2 having some delay if it is generated by counter.

Anyone can telll me how to do and what to do from your experience!?

also How could i check setup and hold time violation which are with respect to clock or clock_div2!??


Thank you in advance

always@smart

routing divided clock in xilinx fpga

As you have a PLL inside the FPGA, I suggest you to use it. That's the right way to generate a new clock. I have not used Altera FPGAs, but usually the internal global clock linex can be sourced by the PLLs. If you are using a FF to divide clock and generate a new clock, it will not have dedicated routing resources to connect it to the global clock lines, because of which you may experience lot of skew in your logic.
You should think of using FF only when you dont have any PLL to spare. If you cant spare a PLL, then using a FF may ot affect you depending on your design, operating frequency etc.

line locked clock fpga

!!!Input clock to PLL has minimum frequency requirement.

For example, Minimum clock for Xilinx spartan II CLK_DLL is 24 MHz. Please check Cyclone's datasheet carefully.

If it just divide by 2, one toggle flipflop is enough. Feed an output of toggle flipflop to global clock buffer for better clock distribution.

clock devider

hai


write code like this


library ieee;
use ieee.std_logic_1164.all;

-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
library UNISIM;
use UNISIM.VComponents.all;

entity clkdll_divide is
port (
clk_in : in std_logic;
clk_out : out std_logic
);
end clkdll_divide;


architecture Behavioral of clkdll_divide is

component CLKDLL
generic (CLKDV_DIVIDE : real);
port (
CLKIN, CLKFB, RST : in STD_LOGIC;
CLK0, CLK90, CLK180, CLK270, CLK2X, CLKDV, LOCKED : out std_logic
);
end component;

component IBUFG
port (
I : in std_logic;
O : out std_logic
);
end component;

component BUFG
port (
I : in std_logic;
O : out std_logic
);
end component;


signal CLKIN, CLK : std_logic;
signal CLK0, CLKDV : std_logic;
signal gnd, LOCKED : std_logic := '0';


begin

ibufg_1 : IBUFG port map (I => clk_in, O => CLKIN);

clkdll_1 : CLKDLL
generic map (CLKDV_DIVIDE => 5.0) -- for simulation and PAR
port map (CLKIN => CLKIN, CLKFB => CLK, RST => gnd,
CLK0 => CLK0, CLKDV => CLKDV, LOCKED => LOCKED);

clk0_bufg_1 : BUFG port map (I => CLK0, O => CLK);
clkdv_bufg_1 : BUFG port map (I => CLKDV, O => clk_out);


end Behavioral;

divide clock code fpga

Hi,
I agree to it_boy's suggestion to use a PLL if you have one available to use.
If you don't have any PLL available, clock díviding by some counter can be used, but be aware not to load the counters output too heavy ; use the output for the CE signal of your FF instead of driving clk signal dirctly (generate a multi-cycle path for your 'low-speed' logic)
Hope it helped,
Maddin

clock deviders

My reply is not add new but I want to stress on solution supplied by memebers.
The most efficient way is to use the available DLL as it will reduce the skew and has good driving capability as its ouput supplied to dedicated routing buffer, but it has restriction on the minimum input frequency, if this restriction is valied use DLL. If not you can make and divide mechanism but instantiate global buffer from the library and connect the clock output to it.

clk_div2.vhd

Hi,

If you want to use a divided clock and the main cock in the same function, you can use an enable signal.
your process is clocked by the global clock, and you put a condition on the state of the divided clock.
the vhdl code of your process is :

IF clrn = '0' then
q_signal <= '0';
ELSIF clk_div2 = '0' THEN NULL;
ELSIF (clk'EVENT AND clk = '1') THEN
q_signal <= d_input;
END IF;

All the registers of your design will be clocked by the global clk. You'll have no problem with setup time.
:wink:

nota : if you want to use an other divided clock (ex : div3, div7, ....), your divided clock shall be a pulse of one clk period duration and with the frequency you need.

clock output fpga

Hi all,

I have another problem now.

Now i need to generate 2 more clock devider for the external device, so I need 2 high-driving-strength(high-capacitance) output in order to able to drive the external device.

how can i do it? further more what should i do?? Please suggest me..

THankyou in advance.

Regards,
Always@smart

clock devider for ddr3

always@smart said:

Hi all,

I have another problem now.

Now i need to generate 2 more clock devider for the external device, so I need 2 high-driving-strength(high-capacitance) output in order to able to drive the external device.

how can i do it? further more what should i do?? Please suggest me..

THankyou in advance.

Regards,
Always@smart

Click to expand...

Use multi-cycle pathes as mentioned above.

fpga clock devider

Check your FPGA pin output capacitance and drive strength. Is it not suffecient?

fpga proces clock

The Fpga only has LVTTL type I/O pins ......
so i have no choice..

But I read the user manual they should have LVDS I/O pins..Can anyone tell me what are the difference btw LVDS and LVTTL !!?? Which one has higher driving-strength??

Thank you in advance.

Regards,

Always@smart

entity clockdiv

which FPGA are you using?
In some of the Xilinx FPGAs I have used, the drive current is configurable from 2mA to 24mA.
The outputs can be configurable as LVDS too.

LVDS stands for Low Voltage Differentisl Signalling.
LVTTL is single ended. LVDS clocks will carry one positive line and one negative line.
It is better you understand the requirement of your application to choose between the two.

divide clock in fpga

Hi all,

As mentioned previously,I'm targeting on A!tera Cycl0ne EP1C6 FPga for my design.

Thank you

multi clocks in fpga

According to this
\hxxp://www.altera.com/products/devices/cyclone/features/cyc-diff_single_io.html
EP1C6 has dedicated LVDS Channels. But I dont know if you can configure the output drive current.

clrn0.dll

If you want to use the clock externally, one important thing you may need to take into account. Without a pll or DLL , the delay from register to pad is generally huge( may exceed 10ns). If your design is a high speed one, you need to regard the two clock totally unrelated.

Hi all,

I've already tried to implement both way; using pll and register to get the clock divided by two.

However after the synthesis, the pll results no clock skew, and therefore i got the correct output as rtl code, from the gate-level timing simulation.

but if my design use clock_div_2 from register, there are clock skew btw clk1 and clk2, hence the timing is wrong.I try a few method to constraint it, but still could not get the correct output, anyone knows how?

and also i have another doubt: does the pll design really have no clock skew? what about the net delay btw this 2 clocks domain??

regards,
always@smart

how to use two clock?