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design compiler and benchmarking ?

Do you use any methodology for Benchmarking EDA tools?

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Clunixchit

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Hai there,

I have a project synthesized by Design Compiler way back at university. However I tried the same project with the same old libraries on a perhaps recent Design Compiler, now I'm having 3000 gates less than with the previous version.

I'm wondering if anyone has some pointers to benchmark Design Compiler in various ways so as to deduce the size, timings, performance, critical paths ....

I guess there should be some methodologies related to this kind of benchmarking. However google wasn't fruitfull.
 

Clunixchit said:
I'm wondering if anyone has some pointers to benchmark Design Compiler in various ways so as to deduce the size, timings, performance, critical paths ....
Click to expand...

report_timing, report_area, and report_power?
 

Thanks, I've figured that out from the DC manuals,

however are there some (standard/well-known) methodologies to be employed in order to benchmark EDA tools ?
 

Well, for something like design compiler, the standard benchmarking method is to do the following:

1. Take a design
2. Compile it
3. Measure how long it took to synthesize and how much memory (RAM) it used
4. Measure the speed, power, and area of the synthesized design
5. Choose a new design and go to (2)

Benchmarking most EDA tools generally comes down to this type of process. If you were benchmarking a SPICE simulator, then your performance metrics would probably be total simulation time, and how easy it is to get the simulation to converge. If you were benchmarking a FastSPICE simulator, then your performance metrics would be the same, plus the accuracy of the simulator (compared to a normal SPICE simulator).
 

Some of the people at our company have started synthesis with RTL compiler and we are seeing some improved benchmark results with it, against Design Compiler. Designs that were not able to meet timing with DC are now meeting with rtl-c.

Does anybody have any feedback on RTL Compiler? There was a survey on EETimes and it seems like rtl-c seems to be very popular

**broken link removed**
As an electronic design automation software user please vote for the RTL synthesis tool that you think is best:

Synopsys Design Compiler 28%
Cadence RTL Compiler 54%
Magma Blast Create 10%
Incentia DesignCraft 7%

What is everybody's thoughts on this?
-- ay
 

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