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DFT : parallel pattern simualation fail. but the serial patt

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VLSI17

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Hi,

I have a design in which there are no scan flops.
I have generated the serial and parallel patterns in FASTSCAN(mentor tool)
On simulating this, the serial patterns pass while the parallel patterns fail.
I feel that, since there are no scan flops in the design, the tool is not able to force the values .
Which is causing the simualtion to fail.

Please let me know if my understanding is right or wrong.
 

Re: DFT : parallel pattern simualation fail. but the serial

Check with Parallel test bench.
 

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