Front end Asic flow question

asic sanity checks

Guys,
I have a question. Assume we have a design we have checked its functnality with respect to Spec with the help of RTL simulations. Now we synthesized the design. Then I did functinol Verification to ensure that RTL and netlist both are functnlly same. Timings we have checked with STA. Assume my constraints are proper in STA and FV and there is no doubt about it.

Now the question is What is the need of Gate Level Simulation then?


Note : STA constraints and FV constraints are proper and there is not doubt about it.

hi vikas,

by static checks, ie. STA for timing verification and Formal Verification for RTL to netlist consistency, then you are "close" to not doing gate level simuation.

You also would need to check the clock domain crossings to ensure that there are no metastability. This can be done with Structural checking tools like Conformal-CDC (which comes built in with your LEC tool) or Real-Intent Clock Verification tool.

However, most people do gate level simulations as a sanity check to make sure that their designs behave cleanly and experience the pleasure of seeing waveforms and catching any glaring mistakes. Moreover, your formal-FV or STA may be constrained (ie. Scan disabled etc). Gate-level sims may be fully unconstratined depending on what mode you want to test.

However, any subtle bugs that FV (formal verification) or STA catches are virtually impossible to identify with gate-level sims.

-- ay

Thanks Adam.
U have given a very good reply.
""You also would need to check the clock domain crossings to ensure that there are no metastability.""
About this I would like to stay that while we do STA it automatically takes care of metastability and formal verification for functinolity.I dont think we require any extra tool to check this.
Adam,
One more doubt I have. STA does not checks for Asynchronous paths.I Think In most of design we do have some combo paths also. I think this might be one of the reason for doing GLS.
Does STA take care of glitches?

Vikas

Regarding STA, incase of combo blocks, they r constrained using virtual clocks, which r written as part of the constraints.

Hi sree,
If possible can u explain it in detail?

STA does not reveal glitches.

gate leve simulation on both corners will boost the confidence level for tape out. Also it is very effective to catch some reset, IO issues. It may also catch some STA timing constrain bugs

Added after 10 seconds:

gate leve simulation on both corners will boost the confidence level for tape out. Also it is very effective to catch some reset, IO issues. It may also catch some STA timing constrain bugs

The common reason to go for a gate level simulations are as follows:

* To check if the reset release, initialization sequence and boot up sequences are proper.
* STA tools doesn't verify the asynchronous interfaces.
* Unintended dependencies on initial conditions can be found through GLS
* Good for verifying the functionality and timing of circuits and paths that are not covered by STA tools
* Design changes can lead to incorrect false path/multi cycle path in the design constraints.
* It gives an excellent feeling that the design is implemented correctly


So before shipping a design to tape-out, we run a limited set of gate level simulations.

yes, STA+FORMAL can be equal to GLS in some aspect, but GLS can do more that STA and Formal cann't do.
STA can't check cross clock-domain timing. GLS can check this in some extent.
GLS can reflect the functional and timing informaion of the real chip, Although it may run long time to do so. So we need to select the GLS test case carefully and run necessary test case.