sally wang
Newbie level 5
ques on Verilog HDL
in Verilog HDL, when should I use 'assign', and when use 'always'? Anyone understands this area can help me modify this Verilog code?
module led1(CLK,SMP,OVR,UPL,TRG);
input CLK;
output SMP,OVR,UPL,TRG;
always @ (CLK)
SMP <= 1'b0;
OVR <= 1'b0;
UPL <= 1'b0;
TRG <= 1'b0;
endmodule
in Verilog HDL, when should I use 'assign', and when use 'always'? Anyone understands this area can help me modify this Verilog code?
module led1(CLK,SMP,OVR,UPL,TRG);
input CLK;
output SMP,OVR,UPL,TRG;
always @ (CLK)
SMP <= 1'b0;
OVR <= 1'b0;
UPL <= 1'b0;
TRG <= 1'b0;
endmodule
