Nikolai
Member level 3
warning:xst:2404
Im am getting the above warning in my design and the output is constantly 0;
The following is my code for a 'rotator' from DCT signal flow graph proposed by Loeffler. (Q7 data format)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Quad_multiplier_A1 is
Port ( IN1 : in STD_LOGIC_VECTOR (7 downto 0);
IN2 : in STD_LOGIC_VECTOR (7 downto 0);
OUT1 : out STD_LOGIC_VECTOR (7 downto 0);
OUT2 : out STD_LOGIC_VECTOR (7 downto 0);
OE : in STD_LOGIC);
end Quad_multiplier_A1;
architecture Behavioral of Quad_multiplier_A1 is
Signal Cn : std_logic_vector (7 downto 0) := "01111101"; -- 0.980
Signal Sn : std_logic_vector (7 downto 0):= "00011001"; -- 0.195
Signal Mul_result_1 : std_logic_vector (15 downto 0);
Signal Mul_result_2 : std_logic_vector (15 downto 0);
Signal Mul_result_3 : std_logic_vector (15 downto 0);
Signal Mul_result_4 : std_logic_vector (15 downto 0);
Signal Add_result_1 : std_logic_vector (7 downto 0) ;
Signal Add_result_2 : std_logic_vector (7 downto 0);
Signal Temp1 : std_logic_vector (15 downto 0); -- to store before left shifting once
Signal Temp2 : std_logic_vector (15 downto 0); -- ,,
Signal Temp3 : std_logic_vector (15 downto 0); -- ,,
Signal Temp4 : std_logic_vector (15 downto 0); -- ,,
Signal Temp5 : std_logic_vector (7 downto 0); -- to store before right shifting once
Signal Temp6 : std_logic_vector (7 downto 0); -- ,,
begin
Temp1 <= IN1 * Cn;
Temp2 <= IN2 * Sn;
Temp3 <= IN1 * Sn;
Temp4 <= IN2 * Cn;
Mul_result_1 <= Temp1 (14 downto 0) & '0';
Mul_result_2 <= Temp2 (14 downto 0) & '0';
Mul_result_3 <= Temp3 (14 downto 0) & '0'; -- left shifting multiplication result
Mul_result_4 <= Temp4 (14 downto 0) & '0';
Temp5 <= Mul_result_1 (15 downto 8) + Mul_result_2 (15 downto 8); -- adding MSB
Temp6 <= Mul_result_4 (15 downto 8) - Mul_result_3 (15 downto 8); -- discarding LSB
Add_result_1 <= '0' & Temp5 (7 downto 1);
Add_result_2 <= '0' & Temp6 (7 downto 1);
OUT1 <= Add_result_1 when (OE'event and OE = '1');
OUT2 <= Add_result_2 when (OE'event and OE = '1');
end Behavioral;
Now here's the synthesis report
Release 9.1i - xst J.30
Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to ./xst/projnav.tmp
CPU : 0.00 / 1.44 s | Elapsed : 0.00 / 2.00 s
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 1.45 s | Elapsed : 0.00 / 2.00 s
--> Reading design: Quad_multiplier_A1.prj
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
3) Design Hierarchy Analysis
4) HDL Analysis
5) HDL Synthesis
5.1) HDL Synthesis Report
6) Advanced HDL Synthesis
6.1) Advanced HDL Synthesis Report
7) Low Level Synthesis
8) Partition Report
9) Final Report
9.1) Device utilization summary
9.2) Partition Resource Summary
9.3) TIMING REPORT
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input File Name : "Quad_multiplier_A1.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "Quad_multiplier_A1"
Output Format : NGC
Target Device : xc2s200-5-pq208
---- Source Options
Top Module Name : Quad_multiplier_A1
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : lut
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Mux Style : Auto
Decoder Extraction : YES
Priority Encoder Extraction : YES
Shift Register Extraction : YES
Logical Shifter Extraction : YES
XOR Collapsing : YES
ROM Style : Auto
Mux Extraction : YES
Resource Sharing : YES
Asynchronous To Synchronous : NO
Multiplier Style : lut
Automatic Register Balancing : No
---- Target Options
Add IO Buffers : YES
Global Maximum Fanout : 100
Add Generic Clock Buffer(BUFG) : 4
Register Duplication : YES
Slice Packing : YES
Optimize Instantiated Primitives : NO
Convert Tristates To Logic : Yes
Use Clock Enable : Yes
Use Synchronous Set : Yes
Use Synchronous Reset : Yes
Pack IO Registers into IOBs : auto
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Library Search Order : Quad_multiplier_A1.lso
Keep Hierarchy : NO
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
Verilog 2001 : YES
Auto BRAM Packing : NO
Slice Utilization Ratio Delta : 5
=========================================================================
=========================================================================
* HDL Compilation *
=========================================================================
Compiling vhdl file "C:/MyProjects/VHDL/Daedalus/Quad_multiplier_A1/Quad_multiplier_A1.vhd" in Library work.
Entity <quad_multiplier_a1> compiled.
Entity <quad_multiplier_a1> (Architecture <behavioral>) compiled.
=========================================================================
* Design Hierarchy Analysis *
=========================================================================
Analyzing hierarchy for entity <Quad_multiplier_A1> in library <work> (architecture <behavioral>).
=========================================================================
* HDL Analysis *
=========================================================================
Analyzing Entity <Quad_multiplier_A1> in library <work> (Architecture <behavioral>).
Entity <Quad_multiplier_A1> analyzed. Unit <Quad_multiplier_A1> generated.
=========================================================================
* HDL Synthesis *
=========================================================================
Performing bidirectional port resolution...
Synthesizing Unit <Quad_multiplier_A1>.
Related source file is "C:/MyProjects/VHDL/Daedalus/Quad_multiplier_A1/Quad_multiplier_A1.vhd".
WARNING:Xst:646 - Signal <Temp1<15>> is assigned but never used.
WARNING:Xst:646 - Signal <Temp2<15>> is assigned but never used.
WARNING:Xst:646 - Signal <Temp3<15>> is assigned but never used.
WARNING:Xst:646 - Signal <Temp4<15>> is assigned but never used.
WARNING:Xst:646 - Signal <Temp5<0>> is assigned but never used.
WARNING:Xst:646 - Signal <Temp6<0>> is assigned but never used.
WARNING:Xst:653 - Signal <Cn> is used but never assigned. Tied to value 01111101.
WARNING:Xst:646 - Signal <Mul_result_1<7:0>> is assigned but never used.
WARNING:Xst:646 - Signal <Mul_result_2<7:0>> is assigned but never used.
WARNING:Xst:646 - Signal <Mul_result_3<7:0>> is assigned but never used.
WARNING:Xst:646 - Signal <Mul_result_4<7:0>> is assigned but never used.
WARNING:Xst:653 - Signal <Sn> is used but never assigned. Tied to value 00011001.
WARNING:Xst - Property "use_dsp48" is not applicable for this technology.
WARNING:Xst - Property "use_dsp48" is not applicable for this technology.
Found 8-bit register for signal <OUT1>.
Found 8-bit register for signal <OUT2>.
Found 8x8-bit multiplier for signal <Temp1>.
Found 8x8-bit multiplier for signal <Temp2>.
Found 8x8-bit multiplier for signal <Temp3>.
Found 8x8-bit multiplier for signal <Temp4>.
Found 8-bit adder for signal <Temp5>.
Found 8-bit subtractor for signal <Temp6>.
Summary:
inferred 16 D-type flip-flop(s).
inferred 2 Adder/Subtractor(s).
inferred 4 Multiplier(s).
Unit <Quad_multiplier_A1> synthesized.
=========================================================================
HDL Synthesis Report
Macro Statistics
# Multipliers : 4
8x8-bit multiplier : 4
# Adders/Subtractors : 2
8-bit adder : 1
8-bit subtractor : 1
# Registers : 2
8-bit register : 2
=========================================================================
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
Loading device for application Rf_Device from file 'v200.nph' in environment C:\Xilinx91i.
WARNING:Xst:2404 - FFs/Latches <OUT1<7:7>> (without init value) have a constant value of 0 in block <Quad_multiplier_A1>.
WARNING:Xst:2404 - FFs/Latches <OUT2<7:7>> (without init value) have a constant value of 0 in block <Quad_multiplier_A1>.
=========================================================================
Advanced HDL Synthesis Report
Macro Statistics
# Multipliers : 4
8x8-bit multiplier : 4
# Adders/Subtractors : 2
8-bit adder : 1
8-bit subtractor : 1
# Registers : 14
Flip-Flops : 14
=========================================================================
=========================================================================
* Low Level Synthesis *
=========================================================================
Optimizing unit <Quad_multiplier_A1> ...
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block Quad_multiplier_A1, actual ratio is 4.
Final Macro Processing ...
=========================================================================
Final Register Report
Macro Statistics
# Registers : 14
Flip-Flops : 14
=========================================================================
=========================================================================
* Partition Report *
=========================================================================
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : Quad_multiplier_A1.ngr
Top Level Output File Name : Quad_multiplier_A1
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs : 33
Cell Usage :
# BELS : 502
# GND : 1
# INV : 32
# LUT1 : 30
# LUT2 : 114
# MUXCY : 174
# VCC : 1
# XORCY : 150
# FlipFlops/Latches : 14
# FD : 14
# Clock Buffers : 1
# BUFGP : 1
# IO Buffers : 32
# IBUF : 16
# OBUF : 16
=========================================================================
Device utilization summary:
---------------------------
Selected Device : 2s200pq208-5
Number of Slices: 102 out of 2352 4%
Number of 4 input LUTs: 176 out of 4704 3%
Number of IOs: 33
Number of bonded IOBs: 33 out of 140 23%
IOB Flip Flops: 14
Number of GCLKs: 1 out of 4 25%
---------------------------
Partition Resource Summary:
---------------------------
No Partitions were found in this design.
---------------------------
=========================================================================
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
OE | BUFGP | 14 |
-----------------------------------+------------------------+-------+
Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design
Timing Summary:
---------------
Speed Grade: -5
Minimum period: No path found
Minimum input arrival time before clock: 17.208ns
Maximum output required time after clock: 7.999ns
Maximum combinational path delay: No path found
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'OE'
Total number of paths / destination ports: 97002 / 14
-------------------------------------------------------------------------
Offset: 17.208ns (Levels of Logic = 17)
Source: IN1<7> (PAD)
Destination: OUT1_6 (FF)
Destination Clock: OE rising
Data Path: IN1<7> to OUT1_6
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 5 0.924 1.740 IN1_7_IBUF (IN1_7_IBUF)
INV:I->O 2 0.653 1.340 IN1<7>_inv1_INV_0 (IN1<7>_inv)
LUT2:I1->O 1 0.653 0.000 Mmult_Temp1_Madd_lut<4> (N32)
MUXCY:S->O 1 0.784 0.000 Mmult_Temp1_Madd_cy<4> (Mmult_Temp1_Madd_cy<4>)
MUXCY:CI->O 1 0.050 0.000 Mmult_Temp1_Madd_cy<5> (Mmult_Temp1_Madd_cy<5>)
MUXCY:CI->O 1 0.050 0.000 Mmult_Temp1_Madd_cy<6> (Mmult_Temp1_Madd_cy<6>)
XORCY:CI->O 4 0.500 1.600 Mmult_Temp1_Madd_xor<7> (Mmult_Temp1_Madd_10)
LUT2:I1->O 1 0.653 0.000 Mmult_Temp1_Madd4_lut<10> (N84)
MUXCY:S->O 1 0.784 0.000 Mmult_Temp1_Madd4_cy<10> (Mmult_Temp1_Madd4_cy<10>)
MUXCY:CI->O 1 0.050 0.000 Mmult_Temp1_Madd4_cy<11> (Mmult_Temp1_Madd4_cy<11>)
XORCY:CI->O 1 0.500 1.150 Mmult_Temp1_Madd4_xor<12> (Mmult_Temp1_Madd_124)
LUT2:I1->O 1 0.653 0.000 Mmult_Temp1_Madd5_lut<12> (N128)
MUXCY:S->O 1 0.784 0.000 Mmult_Temp1_Madd5_cy<12> (Mmult_Temp1_Madd5_cy<12>)
XORCY:CI->O 1 0.500 1.150 Mmult_Temp1_Madd5_xor<13> (Temp1<13>)
LUT2:I0->O 1 0.653 0.000 Madd_Temp5_lut<6> (N149)
MUXCY:S->O 0 0.784 0.000 Madd_Temp5_cy<6> (Madd_Temp5_cy<6>)
XORCY:CI->O 1 0.500 0.000 Madd_Temp5_xor<7> (Temp5<7>)
FD 0.753 OUT1_6
----------------------------------------
Total 17.208ns (10.228ns logic, 6.980ns route)
(59.4% logic, 40.6% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'OE'
Total number of paths / destination ports: 14 / 14
-------------------------------------------------------------------------
Offset: 7.999ns (Levels of Logic = 1)
Source: OUT1_6 (FF)
Destination: OUT1<6> (PAD)
Source Clock: OE rising
Data Path: OUT1_6 to OUT1<6>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FD:C->Q 1 1.292 1.150 OUT1_6 (OUT1_6)
OBUF:I->O 5.557 OUT1_6_OBUF (OUT1<6>)
----------------------------------------
Total 7.999ns (6.849ns logic, 1.150ns route)
(85.6% logic, 14.4% route)
=========================================================================
CPU : 9.31 / 10.86 s | Elapsed : 9.00 / 11.00 s
-->
Total memory usage is 129724 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 16 ( 0 filtered)
Number of infos : 0 ( 0 filtered)
Now i dont understand the warning in the Advanced HDL synthesis. N so even my output is wrong.
Any ideas ?
Im am getting the above warning in my design and the output is constantly 0;
The following is my code for a 'rotator' from DCT signal flow graph proposed by Loeffler. (Q7 data format)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Quad_multiplier_A1 is
Port ( IN1 : in STD_LOGIC_VECTOR (7 downto 0);
IN2 : in STD_LOGIC_VECTOR (7 downto 0);
OUT1 : out STD_LOGIC_VECTOR (7 downto 0);
OUT2 : out STD_LOGIC_VECTOR (7 downto 0);
OE : in STD_LOGIC);
end Quad_multiplier_A1;
architecture Behavioral of Quad_multiplier_A1 is
Signal Cn : std_logic_vector (7 downto 0) := "01111101"; -- 0.980
Signal Sn : std_logic_vector (7 downto 0):= "00011001"; -- 0.195
Signal Mul_result_1 : std_logic_vector (15 downto 0);
Signal Mul_result_2 : std_logic_vector (15 downto 0);
Signal Mul_result_3 : std_logic_vector (15 downto 0);
Signal Mul_result_4 : std_logic_vector (15 downto 0);
Signal Add_result_1 : std_logic_vector (7 downto 0) ;
Signal Add_result_2 : std_logic_vector (7 downto 0);
Signal Temp1 : std_logic_vector (15 downto 0); -- to store before left shifting once
Signal Temp2 : std_logic_vector (15 downto 0); -- ,,
Signal Temp3 : std_logic_vector (15 downto 0); -- ,,
Signal Temp4 : std_logic_vector (15 downto 0); -- ,,
Signal Temp5 : std_logic_vector (7 downto 0); -- to store before right shifting once
Signal Temp6 : std_logic_vector (7 downto 0); -- ,,
begin
Temp1 <= IN1 * Cn;
Temp2 <= IN2 * Sn;
Temp3 <= IN1 * Sn;
Temp4 <= IN2 * Cn;
Mul_result_1 <= Temp1 (14 downto 0) & '0';
Mul_result_2 <= Temp2 (14 downto 0) & '0';
Mul_result_3 <= Temp3 (14 downto 0) & '0'; -- left shifting multiplication result
Mul_result_4 <= Temp4 (14 downto 0) & '0';
Temp5 <= Mul_result_1 (15 downto 8) + Mul_result_2 (15 downto 8); -- adding MSB
Temp6 <= Mul_result_4 (15 downto 8) - Mul_result_3 (15 downto 8); -- discarding LSB
Add_result_1 <= '0' & Temp5 (7 downto 1);
Add_result_2 <= '0' & Temp6 (7 downto 1);
OUT1 <= Add_result_1 when (OE'event and OE = '1');
OUT2 <= Add_result_2 when (OE'event and OE = '1');
end Behavioral;
Now here's the synthesis report
Release 9.1i - xst J.30
Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to ./xst/projnav.tmp
CPU : 0.00 / 1.44 s | Elapsed : 0.00 / 2.00 s
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 1.45 s | Elapsed : 0.00 / 2.00 s
--> Reading design: Quad_multiplier_A1.prj
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
3) Design Hierarchy Analysis
4) HDL Analysis
5) HDL Synthesis
5.1) HDL Synthesis Report
6) Advanced HDL Synthesis
6.1) Advanced HDL Synthesis Report
7) Low Level Synthesis
8) Partition Report
9) Final Report
9.1) Device utilization summary
9.2) Partition Resource Summary
9.3) TIMING REPORT
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input File Name : "Quad_multiplier_A1.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "Quad_multiplier_A1"
Output Format : NGC
Target Device : xc2s200-5-pq208
---- Source Options
Top Module Name : Quad_multiplier_A1
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : lut
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Mux Style : Auto
Decoder Extraction : YES
Priority Encoder Extraction : YES
Shift Register Extraction : YES
Logical Shifter Extraction : YES
XOR Collapsing : YES
ROM Style : Auto
Mux Extraction : YES
Resource Sharing : YES
Asynchronous To Synchronous : NO
Multiplier Style : lut
Automatic Register Balancing : No
---- Target Options
Add IO Buffers : YES
Global Maximum Fanout : 100
Add Generic Clock Buffer(BUFG) : 4
Register Duplication : YES
Slice Packing : YES
Optimize Instantiated Primitives : NO
Convert Tristates To Logic : Yes
Use Clock Enable : Yes
Use Synchronous Set : Yes
Use Synchronous Reset : Yes
Pack IO Registers into IOBs : auto
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Library Search Order : Quad_multiplier_A1.lso
Keep Hierarchy : NO
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
Verilog 2001 : YES
Auto BRAM Packing : NO
Slice Utilization Ratio Delta : 5
=========================================================================
=========================================================================
* HDL Compilation *
=========================================================================
Compiling vhdl file "C:/MyProjects/VHDL/Daedalus/Quad_multiplier_A1/Quad_multiplier_A1.vhd" in Library work.
Entity <quad_multiplier_a1> compiled.
Entity <quad_multiplier_a1> (Architecture <behavioral>) compiled.
=========================================================================
* Design Hierarchy Analysis *
=========================================================================
Analyzing hierarchy for entity <Quad_multiplier_A1> in library <work> (architecture <behavioral>).
=========================================================================
* HDL Analysis *
=========================================================================
Analyzing Entity <Quad_multiplier_A1> in library <work> (Architecture <behavioral>).
Entity <Quad_multiplier_A1> analyzed. Unit <Quad_multiplier_A1> generated.
=========================================================================
* HDL Synthesis *
=========================================================================
Performing bidirectional port resolution...
Synthesizing Unit <Quad_multiplier_A1>.
Related source file is "C:/MyProjects/VHDL/Daedalus/Quad_multiplier_A1/Quad_multiplier_A1.vhd".
WARNING:Xst:646 - Signal <Temp1<15>> is assigned but never used.
WARNING:Xst:646 - Signal <Temp2<15>> is assigned but never used.
WARNING:Xst:646 - Signal <Temp3<15>> is assigned but never used.
WARNING:Xst:646 - Signal <Temp4<15>> is assigned but never used.
WARNING:Xst:646 - Signal <Temp5<0>> is assigned but never used.
WARNING:Xst:646 - Signal <Temp6<0>> is assigned but never used.
WARNING:Xst:653 - Signal <Cn> is used but never assigned. Tied to value 01111101.
WARNING:Xst:646 - Signal <Mul_result_1<7:0>> is assigned but never used.
WARNING:Xst:646 - Signal <Mul_result_2<7:0>> is assigned but never used.
WARNING:Xst:646 - Signal <Mul_result_3<7:0>> is assigned but never used.
WARNING:Xst:646 - Signal <Mul_result_4<7:0>> is assigned but never used.
WARNING:Xst:653 - Signal <Sn> is used but never assigned. Tied to value 00011001.
WARNING:Xst - Property "use_dsp48" is not applicable for this technology.
WARNING:Xst - Property "use_dsp48" is not applicable for this technology.
Found 8-bit register for signal <OUT1>.
Found 8-bit register for signal <OUT2>.
Found 8x8-bit multiplier for signal <Temp1>.
Found 8x8-bit multiplier for signal <Temp2>.
Found 8x8-bit multiplier for signal <Temp3>.
Found 8x8-bit multiplier for signal <Temp4>.
Found 8-bit adder for signal <Temp5>.
Found 8-bit subtractor for signal <Temp6>.
Summary:
inferred 16 D-type flip-flop(s).
inferred 2 Adder/Subtractor(s).
inferred 4 Multiplier(s).
Unit <Quad_multiplier_A1> synthesized.
=========================================================================
HDL Synthesis Report
Macro Statistics
# Multipliers : 4
8x8-bit multiplier : 4
# Adders/Subtractors : 2
8-bit adder : 1
8-bit subtractor : 1
# Registers : 2
8-bit register : 2
=========================================================================
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
Loading device for application Rf_Device from file 'v200.nph' in environment C:\Xilinx91i.
WARNING:Xst:2404 - FFs/Latches <OUT1<7:7>> (without init value) have a constant value of 0 in block <Quad_multiplier_A1>.
WARNING:Xst:2404 - FFs/Latches <OUT2<7:7>> (without init value) have a constant value of 0 in block <Quad_multiplier_A1>.
=========================================================================
Advanced HDL Synthesis Report
Macro Statistics
# Multipliers : 4
8x8-bit multiplier : 4
# Adders/Subtractors : 2
8-bit adder : 1
8-bit subtractor : 1
# Registers : 14
Flip-Flops : 14
=========================================================================
=========================================================================
* Low Level Synthesis *
=========================================================================
Optimizing unit <Quad_multiplier_A1> ...
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block Quad_multiplier_A1, actual ratio is 4.
Final Macro Processing ...
=========================================================================
Final Register Report
Macro Statistics
# Registers : 14
Flip-Flops : 14
=========================================================================
=========================================================================
* Partition Report *
=========================================================================
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : Quad_multiplier_A1.ngr
Top Level Output File Name : Quad_multiplier_A1
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs : 33
Cell Usage :
# BELS : 502
# GND : 1
# INV : 32
# LUT1 : 30
# LUT2 : 114
# MUXCY : 174
# VCC : 1
# XORCY : 150
# FlipFlops/Latches : 14
# FD : 14
# Clock Buffers : 1
# BUFGP : 1
# IO Buffers : 32
# IBUF : 16
# OBUF : 16
=========================================================================
Device utilization summary:
---------------------------
Selected Device : 2s200pq208-5
Number of Slices: 102 out of 2352 4%
Number of 4 input LUTs: 176 out of 4704 3%
Number of IOs: 33
Number of bonded IOBs: 33 out of 140 23%
IOB Flip Flops: 14
Number of GCLKs: 1 out of 4 25%
---------------------------
Partition Resource Summary:
---------------------------
No Partitions were found in this design.
---------------------------
=========================================================================
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
OE | BUFGP | 14 |
-----------------------------------+------------------------+-------+
Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design
Timing Summary:
---------------
Speed Grade: -5
Minimum period: No path found
Minimum input arrival time before clock: 17.208ns
Maximum output required time after clock: 7.999ns
Maximum combinational path delay: No path found
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'OE'
Total number of paths / destination ports: 97002 / 14
-------------------------------------------------------------------------
Offset: 17.208ns (Levels of Logic = 17)
Source: IN1<7> (PAD)
Destination: OUT1_6 (FF)
Destination Clock: OE rising
Data Path: IN1<7> to OUT1_6
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 5 0.924 1.740 IN1_7_IBUF (IN1_7_IBUF)
INV:I->O 2 0.653 1.340 IN1<7>_inv1_INV_0 (IN1<7>_inv)
LUT2:I1->O 1 0.653 0.000 Mmult_Temp1_Madd_lut<4> (N32)
MUXCY:S->O 1 0.784 0.000 Mmult_Temp1_Madd_cy<4> (Mmult_Temp1_Madd_cy<4>)
MUXCY:CI->O 1 0.050 0.000 Mmult_Temp1_Madd_cy<5> (Mmult_Temp1_Madd_cy<5>)
MUXCY:CI->O 1 0.050 0.000 Mmult_Temp1_Madd_cy<6> (Mmult_Temp1_Madd_cy<6>)
XORCY:CI->O 4 0.500 1.600 Mmult_Temp1_Madd_xor<7> (Mmult_Temp1_Madd_10)
LUT2:I1->O 1 0.653 0.000 Mmult_Temp1_Madd4_lut<10> (N84)
MUXCY:S->O 1 0.784 0.000 Mmult_Temp1_Madd4_cy<10> (Mmult_Temp1_Madd4_cy<10>)
MUXCY:CI->O 1 0.050 0.000 Mmult_Temp1_Madd4_cy<11> (Mmult_Temp1_Madd4_cy<11>)
XORCY:CI->O 1 0.500 1.150 Mmult_Temp1_Madd4_xor<12> (Mmult_Temp1_Madd_124)
LUT2:I1->O 1 0.653 0.000 Mmult_Temp1_Madd5_lut<12> (N128)
MUXCY:S->O 1 0.784 0.000 Mmult_Temp1_Madd5_cy<12> (Mmult_Temp1_Madd5_cy<12>)
XORCY:CI->O 1 0.500 1.150 Mmult_Temp1_Madd5_xor<13> (Temp1<13>)
LUT2:I0->O 1 0.653 0.000 Madd_Temp5_lut<6> (N149)
MUXCY:S->O 0 0.784 0.000 Madd_Temp5_cy<6> (Madd_Temp5_cy<6>)
XORCY:CI->O 1 0.500 0.000 Madd_Temp5_xor<7> (Temp5<7>)
FD 0.753 OUT1_6
----------------------------------------
Total 17.208ns (10.228ns logic, 6.980ns route)
(59.4% logic, 40.6% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'OE'
Total number of paths / destination ports: 14 / 14
-------------------------------------------------------------------------
Offset: 7.999ns (Levels of Logic = 1)
Source: OUT1_6 (FF)
Destination: OUT1<6> (PAD)
Source Clock: OE rising
Data Path: OUT1_6 to OUT1<6>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FD:C->Q 1 1.292 1.150 OUT1_6 (OUT1_6)
OBUF:I->O 5.557 OUT1_6_OBUF (OUT1<6>)
----------------------------------------
Total 7.999ns (6.849ns logic, 1.150ns route)
(85.6% logic, 14.4% route)
=========================================================================
CPU : 9.31 / 10.86 s | Elapsed : 9.00 / 11.00 s
-->
Total memory usage is 129724 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 16 ( 0 filtered)
Number of infos : 0 ( 0 filtered)
Now i dont understand the warning in the Advanced HDL synthesis. N so even my output is wrong.
Any ideas ?