filmaker83
Newbie level 5
Now i'm developing com-1000 board, i want to realize a FIR FILTER ad hoc. I'm using matlab for create a .coe file and xilinx ip core generator filter compiler v3.2 for implementing filter. I have write vhdl code for communicate with connectors J1,J2 etc, actmel micro controller and other componensts in the board, now i'm adding filter.xco created from core generator.
My problem is about I/O in the block of filter generated from IP core generator. I would the same bit lenght of the input, in output, for connections I/O.
In input i have DATA_IN [9 0] and instead DATA_OUT [30 0].
I would [9 0] for output!
FILTER is a FIR 21 TAPS with MAC, is there a solution for truncate bit?
My problem is about I/O in the block of filter generated from IP core generator. I would the same bit lenght of the input, in output, for connections I/O.
In input i have DATA_IN [9 0] and instead DATA_OUT [30 0].
I would [9 0] for output!
FILTER is a FIR 21 TAPS with MAC, is there a solution for truncate bit?