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A product Engineer has the responsibility of an IC once it is fabricated. The PE would not be involved with the design nor the Wafer Fabrication Process but is the interface between the manufacture of the IC and the final customer.
The first responsibility is usually with the probing of the IC. The PE may be responsible for the Probe Test, the Probe Program, Interpretation of Probe Test failure, Probe Test parametric shifts (SPC), Probe Tester operations (perhaps maintenance) and calibration.
The PE would need to know how the IC works at least from a block functionality, how it is used in the final application, be familiar with the datasheet and know what test binning parameters correspond to what functionality within the chip.
If a chip fails probe, the PE would look at the binning parameters, what passed and what failed and then make a judgement as to what part of the device is failing. He would then take this information to the wafer fab device engineer and work with that person to determine if the most likely failure was wafer fabrication or IC assembly. If wafer fabrication, the PE hands off the responsibility to the fab Device Engineer. If is is assembly related, the PE is responsible for co-ordinating with the Assembly Process Engineers to determine root cause.
The PE might also be required to modify the Probe Program either the add binning parameters to screen for newly discovered sensitivities that might compromise the device in its application, or more likely to assist in the debug of a wafer fab problem.
The PE is probably to easiest target for the wrath of a customer that has a product fail because os an IC failure or an IC sensitivity not screened at probe. This is the most painful part of the job. Sometimes their is a Field Engineering froup to shield the PE but not often. The PE would be expected to find the route cause and prevent re-occurance. This would normally be done in two steps (the customer only seeing one fix). 1st screen out the newly discovered sensitivity by modifying the probe program or working with Device Engineering to screen it out at wafer level parametric probe. However it is done, it needs to be done asap - or loose the customer. 2nd part of fix is to find route cause and corrrect it properly. This might also involve liasing with the Design Group to implement a robust fix.
Another area of responsibility is cost. Its like an air traffic controller. The idea is once an aeroplane is passed into your responsibility (by that damn device guy), your role is to pass that responsibility onto someone else as quick as possible.
The way to do this is by optimising the IC test flow to be as fast as possible, which means any given IC spends less time in Product Engineering domain and therefore accumulates less cost. So balancing test coverage (I want to test the IC for everything possible to protect me from irate customers) with cost (the more and longer the IC is tested, the more expensive it is - which makes for an irate customer).
The PE should be very familiar with Statistical Process Control (Cp, Cpk etc) and use SPC to detect changes of shifts in IC test behaviours that might predict something bad is going to happen, allowing Engineering to do something about it, before it does. Calibration of testers is important here because if one tester drifts off relative to the others, the line may be shut down for an IC problem that doesn't exist, just sloppy tester matching.
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Added after 1 minutes:
A product Engineer has the responsibility of an IC once it is fabricated. The PE would not be involved with the design nor the Wafer Fabrication Process but is the interface between the manufacture of the IC and the final customer.
The first responsibility is usually with the probing of the IC. The PE may be responsible for the Probe Test, the Probe Program, Interpretation of Probe Test failure, Probe Test parametric shifts (SPC), Probe Tester operations (perhaps maintenance) and calibration.
The PE would need to know how the IC works at least from a block functionality, how it is used in the final application, be familiar with the datasheet and know what test binning parameters correspond to what functionality within the chip.
If a chip fails probe, the PE would look at the binning parameters, what passed and what failed and then make a judgement as to what part of the device is failing. He would then take this information to the wafer fab device engineer and work with that person to determine if the most likely failure was wafer fabrication or IC assembly. If wafer fabrication, the PE hands off the responsibility to the fab Device Engineer. If is is assembly related, the PE is responsible for co-ordinating with the Assembly Process Engineers to determine root cause.
The PE might also be required to modify the Probe Program either the add binning parameters to screen for newly discovered sensitivities that might compromise the device in its application, or more likely to assist in the debug of a wafer fab problem.
The PE is probably to easiest target for the wrath of a customer that has a product fail because os an IC failure or an IC sensitivity not screened at probe. This is the most painful part of the job. Sometimes their is a Field Engineering froup to shield the PE but not often. The PE would be expected to find the route cause and prevent re-occurance. This would normally be done in two steps (the customer only seeing one fix). 1st screen out the newly discovered sensitivity by modifying the probe program or working with Device Engineering to screen it out at wafer level parametric probe. However it is done, it needs to be done asap - or loose the customer. 2nd part of fix is to find route cause and corrrect it properly. This might also involve liasing with the Design Group to implement a robust fix.
Another area of responsibility is cost. Its like an air traffic controller. The idea is once an aeroplane is passed into your responsibility (by that damn device guy), your role is to pass that responsibility onto someone else as quick as possible.
The way to do this is by optimising the IC test flow to be as fast as possible, which means any given IC spends less time in Product Engineering domain and therefore accumulates less cost. So balancing test coverage (I want to test the IC for everything possible to protect me from irate customers) with cost (the more and longer the IC is tested, the more expensive it is - which makes for an irate customer).
The PE should be very familiar with Statistical Process Control (Cp, Cpk etc) and use SPC to detect changes of shifts in IC test behaviours that might predict something bad is going to happen, allowing Engineering to do something about it, before it does. Calibration of testers is important here because if one tester drifts off relative to the others, the line may be shut down for an IC problem that doesn't exist, just sloppy tester matching.
Thnx a lot for giving useful information. can you tell me any kind of interview questions or suggest me the topics that I have to prepare for the interview..
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