jimjim2k
Advanced Member level 3
Hi
A group of students at the Department of Electrical Engineering have designed "ENIAC(TM)-on-a-Chip", under supervision of Professor J. Van der Spiegel, in collaboration with Dr. F. Ketterer. This was done as part of Eniac's 50th Anniversary Celebration. They have integrated the whole "ENIAC" on a 7.44 by 5.29 sq. mm chip using a 0.5 micrometer CMOS technology.
Size: 7.44mm x 5.29mm; 174,569 transistors; 0.5 um CMOS technology (triple metal layer).
1. h**p://pender.ee.upenn.edu/~jan/eniacproj.html
* -> t
tnx
A group of students at the Department of Electrical Engineering have designed "ENIAC(TM)-on-a-Chip", under supervision of Professor J. Van der Spiegel, in collaboration with Dr. F. Ketterer. This was done as part of Eniac's 50th Anniversary Celebration. They have integrated the whole "ENIAC" on a 7.44 by 5.29 sq. mm chip using a 0.5 micrometer CMOS technology.
Size: 7.44mm x 5.29mm; 174,569 transistors; 0.5 um CMOS technology (triple metal layer).
1. h**p://pender.ee.upenn.edu/~jan/eniacproj.html
* -> t
tnx
