Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

What is the hard limiter and the soft limiter?

Status
Not open for further replies.

a_tek7

Banned
Joined
Feb 9, 2006
Messages
161
Helped
11
Reputation
22
Reaction score
2
Trophy points
1,298
Location
Bandar Abbas
Activity points
0
hard limiter circuit

What are the hard Limiter & soft limiter?
 

Re: Hard Limiter?

a_tek7,
A hard limiter produces an output vs input slope of zero (or near zero) at a specied output level. A soft limiter produces a gradual reduction of output vs input slope (dynamic gain) starting at a specified output level.
Regards,
Kral
 

Re: Hard Limiter?

Do you know any circuit to do that?(plz explain ur circuit)

Added after 1 minutes:

thank you.Kral
Do you know any circuit to do that?(plz explain ur circuit)
 

Re: Hard Limiter?

a_tek7

I don't have a schematic drawing tool, so this Viso drawing will have to do. There are two schematics. The top schematic is a hard limiter. It works as follows.
.
When the input voltage is <= VLIM1 and >= VLIM2, the diodes are reverse biased, and the output follows the input. When the input exceeds VLIM1, the diode CR1 is forward biased, and the output is clamped (limited) to the value VLIM1. A similar action takes place when the input is less than (more negative than -VLIM1.
.
The bottom schematic is a soft limiter. It works as follows.
.
When the input is greater than Vlim1, diode CR1 becomes forward biased. R2 and R1 now form a voltage divider, and the slope of the output is equal to R2/(R1+R2).
.
Let Rp be the equivalent of R2 in parallel with R4. Now, when the output voltage exceeds VLIM2, the slope of the output vs input becomes equal to Rp/(R1 + Rp).
.
You can add as many breakpoints as you wish to provide a multi-segment output.
.
This scheme works only if the voltages involved are large enough so that the forward voltage drops across the diodes can be ignored. If this is not the case, then more sophisticated circuits involving op-amps must be used. Let me know if you need and example.
Regards,
Kral

Added after 14 minutes:

a_tek7,
Sorry, the image from my last post did not get properly posted. Here it is:

Regards,
Kral
 
Last edited by a moderator:

Re: Hard Limiter?

Thank you very much kral
if The voltages involved aren't large enough?Do you have any idea?

Added after 1 minutes:

idea about sophisticated circuits involving op-amps must be used
 

Re: Hard Limiter?

a_tek7,
Here is a soft limiter that will work for any signal level, without incurring errors due to diode voltage drops:
.
The bottom circuit, consisting of U2-H4 and associated circuits generates the “curve 2” as shown. Here’s how it works: U2 acts as a non-inverting buffer with a gain of one. The diode CR1 introduces no error because it is inside the negative feedback loop of U1. Vref must be higher than the value of the lower breakpoint of segment 2 of curve 2. The ratio R2/R1 must equal the desired slope (gain) of segment 2 of curve 2. This gain must equal the reciprocal of the desired gain of segment 2 of curve 1. The voltage divider consisting of R3, R4 is such that when the output voltage is equal to the voltage at the bottom of segment 2, the voltage at the NI input of U3 is equal to the voltage at the INV input of U3. At this point, U3 starts to forward bias the diode CR2. This causes U2 to saturate at the negative rail, thus reverse biasing CR1, effectively isolating the output of U2 from the rest of the circuit. The circuit involving U4 operates in the same way for segment 3. The gain of this circuit must equal the reciprocal of the desired slope of segment 3 of curve 1. When U4 starts to forward bias CR3, U3 saturates to the negative rail, thus reverse biasing CR2. Any number of segments can be added in this manner.
.
This network is placed in the feedback loop of U1 as shown. This produces, after the output of U1 is inverted, the output of curve 1.
Regards,
Kral
 
Last edited by a moderator:

    a_tek7

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top