How to come up with calculation of Xilinx System Gate?

Dear all,

Xilinx advertizement or datasheet says about the size of FPGA as System Gate.
Does anyone know how to come up with the calculation of the system gate?
The largest Virtex-II XC2V8000 is about 8 M sytem gates.
Does this mean I can implement 8M logic gates? I guess this is definitely not possible.

Thanks.

xilinx system gates

I too want to find out how to give an exact account for the system gates for a long time.
I know that System gates = Logic Gates + Block Ram bits "+ Routing resources?".
For reference, check Virtex-E datasheet. It describes both System gates and Logic gates saperately.
For XC2V8000, 8M logic gates certainly is not possible. Around 1.2-1.5M Logic gates is my estimate, but it mainly depends on your design.

systemgate lut

Hope this information could help you somehow.

Frag Virtex ASIC equivalent
gates
---------------------------------------
4-input LUT 6
4-input ROM 32
3-input LUT na
16x1 RAM 64
32x1 RAM 128
16 Shift Reg LUT 64
CLB flop 8
CLB latch 5
IOB flop 8
IOB latch 5
IOB Sync latch na
TBUF 3
Block RAM 16,384
BSCAN 48
Clk DLL 7,000
F5 MUX 3
F6 MUX 3
MUXCY 3
XORCY 3

So, One slice contains 2 LUTs or around ~ 12 gates. you could estimate asic gate count based on the number of slices.

system gates xilinx

Does anyone have some information about Altera's System Gates?