shenql
Junior Member level 2
xst:796
hi,everybody
I run a vhdl core on the Modelsim XE 6.2,It's all right!
but when I add this source into ise project ,the problem is coming...
part of core:
getdata
rocess(clk)
type dtype is array (0 to 1535) of integer range 0 to 255;
type text is file of integer ;
file infile: text is in "D:/test3.eti";
variable i:integer:=0;
variable data :dtype;
while (i<1536 )loop
-- the loop for reading the file
read(infile,data(i));
the error is "ERROR:Xst:796 - "D:/Xilinx92i/ETI/ETI.vhdl" line 83: VHDL source expression not yet supported: 'FileDeclaration'."
who know this? please help me, thanks
hi,everybody
I run a vhdl core on the Modelsim XE 6.2,It's all right!
but when I add this source into ise project ,the problem is coming...
part of core:
getdata
rocess(clk)type dtype is array (0 to 1535) of integer range 0 to 255;
type text is file of integer ;
file infile: text is in "D:/test3.eti";
variable i:integer:=0;
variable data :dtype;
while (i<1536 )loop
-- the loop for reading the file
read(infile,data(i));
the error is "ERROR:Xst:796 - "D:/Xilinx92i/ETI/ETI.vhdl" line 83: VHDL source expression not yet supported: 'FileDeclaration'."
who know this? please help me, thanks