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Help with Synplify Modular Design

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fede76pc

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Hi Guys,
I've got a little problem that I know someone (or maybe all) cen solve for me. I have a big VHDL design made of several blocks; it is possible to synthetize each of them independently
and them put them together (I mean the previously single synthetized blocks) in the whole design instead of synthetize the whole design a single time-consuming step.
Thanks a lot 8)
 

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