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what's the use of M5,M6 here??

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devop

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tell me what you think about the circuit:)
thanks
 

i think its function is to improve gain.
 

I think it used to make the current mirror match better.
A pmos and a nmos current mirror together to make the current matching.
But I am not sure. Also to improve the gain.

Best regards!
 

i think it is used to enhance the PM, by reducing the miller Gain
 

I think both {M7 and M5} and {M10 and M6} form cascode configuration that has higher output impedance and so higher gain and also reducing the miller Gain of capacitance at M7 and M10 so better band width... not sure(as in this case it is better to use cascode active load rather than 1 transistor PMOS but may be this is not done to get higher swing).
 

two stage differential to single ended to be exact
 

well - as the g0 of the pmos and of the "cascode" are in parallel in the small signal model - the pmos g0 would dominate the B*gm1*(g0upper||golower) - so there would be nothing to gain by having a nmos cascode and only one pmos towards vdd ...

Added after 5 minutes:

vut when we are into guessing (i haven't even crudely calculated it) - there is a nondominant pole on the node on the left(!!!) side betwen the pmos and the nmos in the symmetrical ota normaly (gmp/(2*pi*cnode)) - by using this configuration one could maybe increase for this pmos-input-stage configuration the phase margin - as already said - by increasing this pole - so that it gets away from th pole at the output node ...

well - only educated guessing ;) (if you have the answer - let m know ;))

Added after 1 minutes:

p.s.: btw. the symmetrical ota is in fact only a one stage type ;)
 

I think they make the matching better thus reduce noise
 

but noise comes mainly from the input diffpair - doesn't it ?
 

Hi, all

I found this ckt in the following paper named Full On Chip CMOS Low-Dropout Voltage Regulator, which is at the following link.
**broken link removed**
 

yschuang said:
Hi, all

I found this ckt in the following paper named Full On Chip CMOS Low-Dropout Voltage Regulator, which is at the following link.
**broken link removed**
Click to expand...
：）yes ,I get the picture form that paper.it's said the M5,M6 is used to reduce the systematic offset and to increase the current mirror accuracy(may caused by other part following the circuit)
can someone explain
 

OTA , but output stage is push-pull stage , like class-AB , have low output impedence
 

make the VDS of M7,10 about the same as
M8,9 to reduce the system offset. You can guess
here, vin is about 3V, vt is about 0.7V given 0.35
um technology.
 

It reduces systematic offset because it forces the same voltage on the drains of M7 and M10. If you removed the NMOS devices, the values of on drains of M7 and M10 and would be reflected right back to the input as a systematic offset.

By putting the NMOS there, it also increase the gain because you basicall have a cascode effect due to the stacked NMOS devices.
 

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