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A DLL is a delay locked loop. Rather than adjust the phase until the error is zero, the output signal is delay with a tapped delay line and the taps are adjusted until the delay error is minimal. Zero error cannot usually be obtained because of the coarseness of the delay steps.
On some DLL systems, the output jitter is worse because the system keeps switching between a tap that is gives too much delay and the adjacent tap that gives too little delay. Other DLLs, sense this jumping back and forth and just pick one or the other.
FPGA vendors can include more DLLs than PLLs because the circuitry is smaller.
Not true.
"Modern" FPGA such as Altera Stratix (1,2 and also 3) have internal PLL.
Moreover a PLL usually have the capability to create a clock that is multiple (also fractional) of the input clock.
Another thing is that a PLL can compensate the Input clock also from a feedback signal.
If need more detail have a look on www.altera.com and look at stratix 2 pll description, they explain almost all you need to know.
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