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my 2 cents about the discussion about spare-cells.
In order to address the last minute changes or need to fix any functional or any timing changes we go for a stage called as ECO[Engineering Change Order].
So at this stage we use the free cells or spare cells during Metal only Fixes.
so what this spare -cells ?
By the name calls these are some extra cells dumped in the chip to help us in order to honour ECO's.
What is the metric or amount of spare-cells to be used?
There is no hard and fast rules , it is totally based on the confidence level of the design as well as the quality of the test-vectors, usuallly around 5% spare-cells will be used as extra cells.
Whether spare-cells will be used in RTL or during implementation stage[place and route]?
Spare-cells could be used in RTL stages manually instantiate a spare-cell modules which has the flavour of the spare-cells.
Or
Use it in the implementation stages, say it in place and route stage now a days placement tools are clever in this concept of spare-cells insertion.
What is the flow i should use RTL spare-cells or implementation based , please guide me.
Using RTL based there is a limitation, that all the cells will be cluttered in a same place and distribution of the cells will not be honoured.
where as in the implementation based the distribution can behonoured.
what should i do with the input of these spare-cells.
The input of these spare-cells need to be tied to zero and not let floating this is very very important otherwise will lead to lot of leakage current which is dangerous for the chip.
What are the flavours of cells i should use for spare-cells.
Usually few flops,buffers,inverters,latch,few clock-gating cells,nor,nand.
how do i ensure that the spare-cells are distributed.
divide the chip in to many rectangles and specify the sparecells in each rectangles so that the distribution of the spare-cells could be controlled and honored.
should i built tree for spare-cell flops as well up front.
you can do this , and this is better, so that in case in future if you want to opt for this flip -flop for ECO then it would be better and you dont want to think on clock-tree balancing of this flip-flop.
hope this answers few doubts and clear the concepts.
Hi vlsichipdesigner,
Thanks alot for your detailed explanation. I have a small question.
Spare Cell inputs are tied to ground using tiegnd cell. Then in this case the output of these cells will be floating right?.
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